首页 零基础DSP实战TMS320F28035：第十节，DSP之CLA内核应用实战.zip

零基础DSP实战TMS320F28035：第十节，DSP之CLA内核应用实战.zip

上传者： sinat_30943509 | 上传时间： 2024-09-25 01:28:37 | 文件大小： 567KB | 文件类型： ZIP
TMS320F28035有两个内核，一个是DSP的CPU内核，一个是控制律加速器（CLA）是一个独立、完全可编程的 32 位浮点数学处理器，它将并行控制环执行功能引入到 C28x 系列器件。CLA 的低中断延迟使得它能即时读取 ADC 采样。这就极大降低了 ADC 采样到输出的延时，实现了更快的系统响应和更高频率的控制回路。通过利用 CLA 来服务对时间要求严格（time-critical）控制回路，主 CPU 就能自由地处理其它诸如通信、诊断之类的系统任务。

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