头歌计算机组成原理所有实验（已通关版）

[{"title":"（ 42 个子文件 2.77MB ） 头歌计算机组成原理所有实验（已通关版）","children":[{"title":"头歌平台试验","children":[{"title":"存储系统设计","children":[{"title":"第4关：全相联cache设计.txt <span style='color:#111;'> 1.03MB </span>","children":null,"spread":false},{"title":"第5关：直接相联cache设计.txt <span style='color:#111;'> 1.03MB </span>","children":null,"spread":false},{"title":"第3关：MIPS RAM设计.txt <span style='color:#111;'> 1.03MB </span>","children":null,"spread":false},{"title":"第2关：MIPS寄存器文件设计.txt <span style='color:#111;'> 1.03MB </span>","children":null,"spread":false},{"title":"第7关：2路组相联cache设计.txt <span style='color:#111;'> 1.03MB </span>","children":null,"spread":false},{"title":"第1关：汉字字库存储芯片扩展实验.txt <span style='color:#111;'> 1.03MB </span>","children":null,"spread":false},{"title":"第6关：4路组相连cache设计.txt <span style='color:#111;'> 1.03MB </span>","children":null,"spread":false}],"spread":true},{"title":"运算器设计","children":[{"title":"第7关：6位有符号补码阵列乘法器.txt <span style='color:#111;'> 540.17KB </span>","children":null,"spread":false},{"title":"第8关：乘法流水线设计.txt <span style='color:#111;'> 540.17KB </span>","children":null,"spread":false},{"title":"第2关：CLA182四位先行进位电路设计.txt <span style='color:#111;'> 540.17KB </span>","children":null,"spread":false},{"title":"第5关：32位快速加法器设计.txt <span style='color:#111;'> 540.17KB </span>","children":null,"spread":false},{"title":"第6关：5位无符号阵列乘法器设计.txt <span style='color:#111;'> 540.17KB </span>","children":null,"spread":false},{"title":"第9关：原码一位乘法器设计.txt <span style='color:#111;'> 540.17KB </span>","children":null,"spread":false},{"title":"第11关：MIPS运算器设计.txt <span style='color:#111;'> 540.17KB </span>","children":null,"spread":false},{"title":"第4关：16位快速加法器设计.txt <span style='color:#111;'> 540.17KB </span>","children":null,"spread":false},{"title":"第10关：补码一位乘法器设计.txt <span style='color:#111;'> 540.17KB </span>","children":null,"spread":false},{"title":"第3关：4位快速加法器设计.txt <span style='color:#111;'> 540.17KB </span>","children":null,"spread":false},{"title":"第1关：8位可控加减法电路设计.txt <span style='color:#111;'> 540.17KB </span>","children":null,"spread":false}],"spread":false},{"title":"MIPS CPU设计(HUST)","children":[{"title":"第3关：MIPS微程序CPU设计.txt <span style='color:#111;'> 347.66KB </span>","children":null,"spread":false},{"title":"第4关：硬布线控制器状态机设计.txt <span style='color:#111;'> 347.66KB </span>","children":null,"spread":false},{"title":"第5关：多周期MIPS硬布线控制器CPU设计（排序程序）.txt <span style='color:#111;'> 270.82KB </span>","children":null,"spread":false},{"title":"第1关：单周期MIPS CPU设计.circ <span style='color:#111;'> 347.66KB </span>","children":null,"spread":false},{"title":"第2关：微程序地址转移逻辑设计.txt <span style='color:#111;'> 347.66KB </span>","children":null,"spread":false}],"spread":true},{"title":"定长CPU设计","children":[{"title":"第6关：定长指令周期---单总线CPU设计.txt <span style='color:#111;'> 537.52KB </span>","children":null,"spread":false},{"title":"第5关：定长指令周期---硬布线控制器设计.txt <span style='color:#111;'> 537.52KB </span>","children":null,"spread":false},{"title":"第3关：定长指令周期---时序发生器输出函数设计.txt <span style='color:#111;'> 537.52KB </span>","children":null,"spread":false},{"title":"MIPS指令译码器设计.txt <span style='color:#111;'> 537.52KB </span>","children":null,"spread":false},{"title":"第4关：硬布线控制器组合逻辑单元.txt <span style='color:#111;'> 537.52KB </span>","children":null,"spread":false},{"title":"第2关：定长指令周期---时序发生器FSM设计.txt <span style='color:#111;'> 537.52KB </span>","children":null,"spread":false}],"spread":true},{"title":"现代时序CPU设计","children":[{"title":"采用微程序的单总线CPU设计.txt <span style='color:#111;'> 679.47KB </span>","children":null,"spread":false},{"title":"现代时序硬布线控制器状态机设计.txt <span style='color:#111;'> 679.47KB </span>","children":null,"spread":false},{"title":"单总线CPU微程序条件判别测试逻辑.txt <span style='color:#111;'> 679.47KB </span>","children":null,"spread":false},{"title":"单总线CPU微程序入口查找逻辑.txt <span style='color:#111;'> 679.47KB </span>","children":null,"spread":false},{"title":"MIPS指令译码器设计.txt <span style='color:#111;'> 679.47KB </span>","children":null,"spread":false},{"title":"现代时序硬布线控制器设计.txt <span style='color:#111;'> 679.47KB </span>","children":null,"spread":false},{"title":"单总线CPU微程序控制器设计.txt <span style='color:#111;'> 679.47KB </span>","children":null,"spread":false}],"spread":true},{"title":"变长指令周期CPU设计","children":[{"title":"变长指令周期---单总线CPU设计.txt <span style='color:#111;'> 521.85KB </span>","children":null,"spread":false},{"title":"变长指令周期---硬布线控制器设计.txt <span style='color:#111;'> 521.85KB </span>","children":null,"spread":false},{"title":"MIPS指令译码器设计.txt <span style='color:#111;'> 521.85KB </span>","children":null,"spread":false},{"title":"变长指令周期---时序发生器FSM设计.txt <span style='color:#111;'> 521.85KB </span>","children":null,"spread":false},{"title":"硬布线控制器组合逻辑单元.txt <span style='color:#111;'> 521.85KB </span>","children":null,"spread":false},{"title":"变长指令周期---时序发生器输出函数设计.txt <span style='color:#111;'> 521.85KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}]