ARM system-on-chip architecture

1.1 Processor architecture and organization 2 1.2 Abstraction in hardware design 3 1.3 MU0 - a simple processor 7 1.4 Instruction set design 14 1.5 Processor design trade-offs 19 1.6 The Reduced Instruction Set Computer 24 1.7 Design for low power consumption 28 1.8 Examples and exercises 32…… 2.1 The Acorn RISC Machine 36 2.2 Architectural inheritance 37 2.3 The ARM programmer's model 39 2.4 ARM development tools 43 2.5 Example and exercises 47…… 3.1 Data processing instructions 50 3.2 Data transfer instructions 55 3.3 Control flow instructions 63 3.4 Writing simple assembly language programs 69 3.5 Examples and exercises 72…… 4.1 3-stage pipeline ARM organization 75 4.2 5-stage pipeline ARM organization 78 4.3 ARM instruction execution 82 4.4 ARM implementation 86 4.5 The ARM coprocessor interface 101 4.6 Examples and exercises 103…… 5.1 Introduction 106 5.2 Exceptions 108 5.3 Conditional execution 111 5.4 Branch and Branch with Link (B, BL) 113 5.5 Branch, Branch with Link and eXchange (BX, BLX) 115 5.6 Software Interrupt (SWI) 117 5.7 Data processing instructions 119 5.8 Multiply instructions 122 5.9 Count leading zeros (CLZ - architecture v5T only) 124 5.10 Single word and unsigned byte data transfer instructions 125 5.11 Half-word and signed byte data transfer instructions 128 5.12 Multiple register transfer instructions 130 5.13 Swap memory and register instructions (SWP) 132 5.14 Status register to general register transfer instructions 133 5.15 General register to status register transfer instructions 134 5.16 Coprocessor instructions 136 5.17 Coprocessor data operations 137 5.18 Coprocessor data transfers 138 5.19 Coprocessor register transfers 139 5.20 Breakpoint instruction (BRK - architecture v5T only) 141 5.21 Unused instruction space 142 5.22 Memory faults 143 5.23 ARM architecture variants 147 5.24 Example and exercises 149…… 6.1 Abstraction in software design 152 6.2 Data types 153 6.3 Floating-point data types 158 6.4 The ARM floating-point archite