[{"title":"( 122 个子文件 3.33MB ) FPGA——UART Rx Verilog程序设计","children":[{"title":"tx_control_module.v.bak <span style='color:#111;'> 1.08KB </span>","children":null,"spread":false},{"title":"rx_control_module.v.bak <span style='color:#111;'> 1.30KB </span>","children":null,"spread":false},{"title":"detect_module.v <span style='color:#111;'> 461B </span>","children":null,"spread":false},{"title":"test_UART.qpf <span style='color:#111;'> 1.26KB </span>","children":null,"spread":false},{"title":"rx_control_module.v <span style='color:#111;'> 1.60KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]