基于FPGA的三速以太网UDP协议栈设计_Tri_Eth_UDP_pro_stack.zip

[{"title":"（ 32 个子文件 75KB ） 基于FPGA的三速以太网UDP协议栈设计_Tri_Eth_UDP_pro_stack.zip","children":[{"title":"Tri_Eth_UDP_pro_stack-main","children":[{"title":"picture","children":[{"title":"UDP_summary.png <span style='color:#111;'> 27.28KB </span>","children":null,"spread":false}],"spread":true},{"title":"tb","children":[{"title":"crc_tb.v <span style='color:#111;'> 1.49KB </span>","children":null,"spread":false},{"title":"SIM_udp_stack_TB.v <span style='color:#111;'> 15.52KB </span>","children":null,"spread":false}],"spread":true},{"title":"rtl","children":[{"title":"ARP_RX.v <span style='color:#111;'> 4.92KB </span>","children":null,"spread":false},{"title":"MAC_IP_ARP_demux.v <span style='color:#111;'> 2.98KB </span>","children":null,"spread":false},{"title":"XC7A100_TOP.v <span style='color:#111;'> 7.50KB </span>","children":null,"spread":false},{"title":"IP_module.v <span style='color:#111;'> 3.97KB </span>","children":null,"spread":false},{"title":"CRC_data_process.v <span style='color:#111;'> 11.29KB </span>","children":null,"spread":false},{"title":"RGMII_RAM.v <span style='color:#111;'> 10.70KB </span>","children":null,"spread":false},{"title":"UDP_module.v <span style='color:#111;'> 3.07KB </span>","children":null,"spread":false},{"title":"MAC_TX.v <span style='color:#111;'> 12.56KB </span>","children":null,"spread":false},{"title":"ICMP_RX.v <span style='color:#111;'> 3.28KB </span>","children":null,"spread":false},{"title":"IP_TX.v <span style='color:#111;'> 9.34KB </span>","children":null,"spread":false},{"title":"MAC_RX.v <span style='color:#111;'> 11.42KB </span>","children":null,"spread":false},{"title":"RGMII_RAM_qi.v <span style='color:#111;'> 10.76KB </span>","children":null,"spread":false},{"title":"RGMII_Tri.v <span style='color:#111;'> 9.68KB </span>","children":null,"spread":false},{"title":"IP_RX.v <span style='color:#111;'> 7.27KB </span>","children":null,"spread":false},{"title":"ARP_module.v <span style='color:#111;'> 3.27KB </span>","children":null,"spread":false},{"title":"ARP_TX.v <span style='color:#111;'> 6.80KB </span>","children":null,"spread":false},{"title":"Ethernet_MAC.v <span style='color:#111;'> 5.56KB </span>","children":null,"spread":false},{"title":"UDP_TX.v <span style='color:#111;'> 7.56KB </span>","children":null,"spread":false},{"title":"GMII2RGMII_drive.v <span style='color:#111;'> 4.13KB </span>","children":null,"spread":false},{"title":"CRC32_D8.v <span style='color:#111;'> 4.02KB </span>","children":null,"spread":false},{"title":"ICMP_TX.v <span style='color:#111;'> 4.79KB </span>","children":null,"spread":false},{"title":"Data_2to1_arbiter.v <span style='color:#111;'> 10.62KB </span>","children":null,"spread":false},{"title":"ICMP_module.v <span style='color:#111;'> 1.70KB </span>","children":null,"spread":false},{"title":"RGMII_Tri_qi.v <span style='color:#111;'> 10.96KB </span>","children":null,"spread":false},{"title":"UDP_RX.v <span style='color:#111;'> 4.29KB </span>","children":null,"spread":false},{"title":"rst_gen_module.v <span style='color:#111;'> 1.06KB </span>","children":null,"spread":false},{"title":"ARP_table.v <span style='color:#111;'> 10.35KB </span>","children":null,"spread":false},{"title":"UDP_Stack_TOP.v <span style='color:#111;'> 12.81KB </span>","children":null,"spread":false}],"spread":false},{"title":"README.md <span style='color:#111;'> 117B </span>","children":null,"spread":false}],"spread":true}],"spread":true}]