spi.zip，verilog编写的RTL、Testbench和tcl文件

[{"title":"（ 6 个子文件 13KB ） spi.zip，verilog编写的RTL、Testbench和tcl文件","children":[{"title":"spi","children":[{"title":".tb_spi.v.swp <span style='color:#111;'> 12.00KB </span>","children":null,"spread":false},{"title":"spi.v <span style='color:#111;'> 8.01KB </span>","children":null,"spread":false},{"title":".spi.v.swo <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"tb_spi.v <span style='color:#111;'> 1.37KB </span>","children":null,"spread":false},{"title":"spi.tcl <span style='color:#111;'> 17.47KB </span>","children":null,"spread":false},{"title":".spi.v.swp <span style='color:#111;'> 16.00KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]