[{"title":"( 9 个子文件 7KB ) AES_加解密_verilog实现.zip","children":[{"title":"新建文件夹","children":[{"title":"testbench_aes128.v <span style='color:#111;'> 307B </span>","children":null,"spread":false},{"title":"substitution_box.v <span style='color:#111;'> 10.40KB </span>","children":null,"spread":false},{"title":"main_decryption128.v <span style='color:#111;'> 1.86KB </span>","children":null,"spread":false},{"title":"timescale.v <span style='color:#111;'> 21B </span>","children":null,"spread":false},{"title":"mix_column.v <span style='color:#111;'> 5.17KB </span>","children":null,"spread":false},{"title":"substitution_byte.v <span style='color:#111;'> 2.02KB </span>","children":null,"spread":false},{"title":"main_encryption128.v <span style='color:#111;'> 2.17KB </span>","children":null,"spread":false},{"title":"shift_row.v <span style='color:#111;'> 1.95KB </span>","children":null,"spread":false},{"title":"Round_keys.v <span style='color:#111;'> 1.04KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]