基于FPGA的fir滤波器verilog

[{"title":"（ 11 个子文件 27KB ） 基于FPGA的fir滤波器verilog","children":[{"title":"fir_13","children":[{"title":"sin_bin.txt <span style='color:#111;'> 27.36KB </span>","children":null,"spread":false},{"title":"FIR.v <span style='color:#111;'> 2.06KB </span>","children":null,"spread":false},{"title":"db","children":[{"title":"fir_13.sld_design_entry.sci <span style='color:#111;'> 223B </span>","children":null,"spread":false},{"title":"fir_13.db_info <span style='color:#111;'> 140B </span>","children":null,"spread":false}],"spread":true},{"title":"pusle_fir.v <span style='color:#111;'> 2.79KB </span>","children":null,"spread":false},{"title":"mult_bb.v <span style='color:#111;'> 3.93KB </span>","children":null,"spread":false},{"title":"test.cr.mti <span style='color:#111;'> 1.00KB </span>","children":null,"spread":false},{"title":"transcript <span style='color:#111;'> 393B </span>","children":null,"spread":false},{"title":"test.mpf <span style='color:#111;'> 73.92KB </span>","children":null,"spread":false},{"title":"FIR_tb.v <span style='color:#111;'> 1.18KB </span>","children":null,"spread":false},{"title":"mult.v <span style='color:#111;'> 4.58KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]