黑金AX301/4010FPGA开发板硬件工程（含原理图及PCB）

[{"title":"（ 33 个子文件 4.95MB ） 黑金AX301/4010FPGA开发板硬件工程（含原理图及PCB）","children":[{"title":"原理图和PCB","children":[{"title":"AX301_AX4010.PcbDoc.htm <span style='color:#111;'> 4.53KB </span>","children":null,"spread":false},{"title":"5_SDRAM.SchDoc <span style='color:#111;'> 78.00KB </span>","children":null,"spread":false},{"title":"7_VGA.SchDoc <span style='color:#111;'> 230.00KB </span>","children":null,"spread":false},{"title":"4_FPGA.SchDoc <span style='color:#111;'> 695.00KB </span>","children":null,"spread":false},{"title":"AX301_AX4010_SCH.PDF <span style='color:#111;'> 139.86KB </span>","children":null,"spread":false},{"title":"3_FPGA.SchDoc <span style='color:#111;'> 419.00KB </span>","children":null,"spread":false},{"title":"AX301_AX4010.PcbDoc <span style='color:#111;'> 3.14MB </span>","children":null,"spread":false},{"title":"1_POWER.SchDoc <span style='color:#111;'> 136.00KB </span>","children":null,"spread":false},{"title":"AX301_AX4010.IntLib <span style='color:#111;'> 607.50KB </span>","children":null,"spread":false},{"title":"debug.log <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"2_FPGA.SchDoc <span style='color:#111;'> 418.50KB </span>","children":null,"spread":false},{"title":"AX301_AX4010.PrjPCB <span style='color:#111;'> 54.28KB </span>","children":null,"spread":false},{"title":"History","children":[{"title":"AX301_AX4010.~(2).PcbDoc.Zip <span style='color:#111;'> 1.14MB </span>","children":null,"spread":false},{"title":"5_SDRAM.~(1).SchDoc.Zip <span style='color:#111;'> 12.40KB </span>","children":null,"spread":false},{"title":"4_FPGA.~(1).SchDoc.Zip <span style='color:#111;'> 73.29KB </span>","children":null,"spread":false},{"title":"6_DIG.~(1).SchDoc.Zip <span style='color:#111;'> 40.14KB </span>","children":null,"spread":false},{"title":"1_POWER.~(1).SchDoc.Zip <span style='color:#111;'> 19.46KB </span>","children":null,"spread":false},{"title":"AX301_AX4010.~(1).PrjPCB.Zip <span style='color:#111;'> 6.22KB </span>","children":null,"spread":false},{"title":"2_FPGA.~(1).SchDoc.Zip <span style='color:#111;'> 45.11KB </span>","children":null,"spread":false},{"title":"4_FPGA.~(2).SchDoc.Zip <span style='color:#111;'> 85.03KB </span>","children":null,"spread":false},{"title":"AX301_AX4010.~(1).PcbDoc.Zip <span style='color:#111;'> 1.14MB </span>","children":null,"spread":false},{"title":"3_FPGA.~(1).SchDoc.Zip <span style='color:#111;'> 45.61KB </span>","children":null,"spread":false},{"title":"7_VGA.~(1).SchDoc.Zip <span style='color:#111;'> 27.63KB </span>","children":null,"spread":false},{"title":"AX301_AX4010.~(2).PrjPCB.Zip <span style='color:#111;'> 6.80KB </span>","children":null,"spread":false}],"spread":false},{"title":"__Previews","children":[{"title":"4_FPGA.SchDocPreview <span style='color:#111;'> 71.86KB </span>","children":null,"spread":false},{"title":"2_FPGA.SchDocPreview <span style='color:#111;'> 75.92KB </span>","children":null,"spread":false},{"title":"3_FPGA.SchDocPreview <span style='color:#111;'> 78.04KB </span>","children":null,"spread":false},{"title":"5_SDRAM.SchDocPreview <span style='color:#111;'> 52.57KB </span>","children":null,"spread":false},{"title":"AX301_AX4010.PcbDocPreview <span style='color:#111;'> 115.52KB </span>","children":null,"spread":false},{"title":"1_POWER.SchDocPreview <span style='color:#111;'> 64.81KB </span>","children":null,"spread":false},{"title":"6_DIG.SchDocPreview <span style='color:#111;'> 82.47KB </span>","children":null,"spread":false},{"title":"7_VGA.SchDocPreview <span style='color:#111;'> 64.47KB </span>","children":null,"spread":false}],"spread":true},{"title":"6_DIG.SchDoc <span style='color:#111;'> 431.50KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]