ARM Cortex-M0 的软微控制器实现_SystemVerilog_代码_相关文件_下载

[{"title":"（ 44 个子文件 58KB ） ARM Cortex-M0 的软微控制器实现_SystemVerilog_代码_相关文件_下载\n\n","children":[{"title":"cortex-m0-soft-microcontroller-master","children":[{"title":".gitmodules <span style='color:#111;'> 1.02KB </span>","children":null,"spread":false},{"title":"ip_cores","children":[{"title":"general-cores","children":null,"spread":false},{"title":"roa_logic","children":[{"title":"ahb3lite_timer","children":null,"spread":false},{"title":"ahb3lite_memory","children":null,"spread":false},{"title":"memory","children":null,"spread":false},{"title":"ahb3lite_interconnect","children":null,"spread":false},{"title":"ahb3lite_pkg","children":null,"spread":false}],"spread":true},{"title":"ahb3lite_dma","children":null,"spread":false},{"title":"vhdl-extras","children":null,"spread":false}],"spread":true},{"title":"top","children":[{"title":"kc705_busy_wait","children":[{"title":"cm0_busy_wait_top.xdc <span style='color:#111;'> 2.41KB </span>","children":null,"spread":false},{"title":"verilog","children":[{"title":"Manifest.py <span style='color:#111;'> 1.05KB </span>","children":null,"spread":false},{"title":"cm0_busy_wait_top.sv <span style='color:#111;'> 15.65KB </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"kc705_dma","children":[{"title":"cm0_dma_top.xdc <span style='color:#111;'> 2.41KB </span>","children":null,"spread":false},{"title":"verilog","children":[{"title":"cm0_dma_top.sv <span style='color:#111;'> 22.75KB </span>","children":null,"spread":false},{"title":"Manifest.py <span style='color:#111;'> 1.16KB </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"kc705_blinky","children":[{"title":"cm0_blinky_top.xdc <span style='color:#111;'> 2.41KB </span>","children":null,"spread":false},{"title":"verilog","children":[{"title":"Manifest.py <span style='color:#111;'> 976B </span>","children":null,"spread":false},{"title":"cm0_blinky_top.sv <span style='color:#111;'> 12.36KB </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"kc705_interruption","children":[{"title":"cm0_interruption_top.xdc <span style='color:#111;'> 2.41KB </span>","children":null,"spread":false},{"title":"verilog","children":[{"title":"Manifest.py <span style='color:#111;'> 1.13KB </span>","children":null,"spread":false},{"title":"cm0_interruption_top.sv <span style='color:#111;'> 16.78KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true},{"title":"LICENSE <span style='color:#111;'> 1.05KB </span>","children":null,"spread":false},{"title":"sim","children":[{"title":"kc705_busy_wait","children":[{"title":"run_busy_wait_sim.tcl <span style='color:#111;'> 218B </span>","children":null,"spread":false}],"spread":true},{"title":"kc705_interrupt","children":[{"title":"run_interrupt_sim.tcl <span style='color:#111;'> 224B </span>","children":null,"spread":false}],"spread":true},{"title":"kc705_dma","children":[{"title":"run_dma_sim.tcl <span style='color:#111;'> 206B </span>","children":null,"spread":false}],"spread":true},{"title":"kc705_blinky","children":[{"title":"run_blinky_sim.tcl <span style='color:#111;'> 212B </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":".gitignore <span style='color:#111;'> 1.71KB </span>","children":null,"spread":false},{"title":"README.md <span style='color:#111;'> 2.31KB </span>","children":null,"spread":false},{"title":"syn","children":[{"title":"kc705_busy_wait","children":[{"title":"verilog","children":[{"title":"Manifest.py <span style='color:#111;'> 260B </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"kc705_dma","children":[{"title":"verilog","children":[{"title":"Manifest.py <span style='color:#111;'> 242B </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"kc705_blinky","children":[{"title":"verilog","children":[{"title":"Manifest.py <span style='color:#111;'> 251B </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"kc705_interruption","children":[{"title":"verilog","children":[{"title":"Manifest.py <span style='color:#111;'> 269B </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true},{"title":"modules","children":[{"title":"misc","children":[{"title":"vhdl","children":[{"title":"Manifest.py <span style='color:#111;'> 62B </span>","children":null,"spread":false},{"title":"detection_fsm.vhd <span style='color:#111;'> 2.78KB </span>","children":null,"spread":false},{"title":"edge_detector.vhd <span style='color:#111;'> 2.85KB </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"cortex-m0","children":[{"title":"vhdl","children":[{"title":"Manifest.py <span style='color:#111;'> 42B </span>","children":null,"spread":false},{"title":"cortex_m0_wrapper.vhd <span style='color:#111;'> 21.93KB </span>","children":null,"spread":false}],"spread":true},{"title":"verilog","children":[{"title":"Manifest.py <span style='color:#111;'> 68B </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"clk","children":[{"title":"vhdl","children":[{"title":"Manifest.py <span style='color:#111;'> 32B </span>","children":null,"spread":false},{"title":"sys_pll.vhd <span style='color:#111;'> 7.64KB </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"memory","children":[{"title":"memory_dma_syn.mem <span style='color:#111;'> 8.28KB </span>","children":null,"spread":false},{"title":"memory_interrupt_sim.mem <span style='color:#111;'> 7.54KB </span>","children":null,"spread":false},{"title":"vhdl","children":[{"title":"rl_ram_1r1w_generic.vhd <span style='color:#111;'> 3.69KB </span>","children":null,"spread":false},{"title":"Manifest.py <span style='color:#111;'> 44B </span>","children":null,"spread":false}],"spread":false},{"title":"memory_interrupt_syn.mem <span style='color:#111;'> 7.54KB </span>","children":null,"spread":false},{"title":"memory_200_sim.mem <span style='color:#111;'> 3.03KB </span>","children":null,"spread":false},{"title":"memory_dma_sim.mem <span style='color:#111;'> 8.28KB </span>","children":null,"spread":false},{"title":"memory_dummy.mem <span style='color:#111;'> 16.50KB </span>","children":null,"spread":false},{"title":"memory_1M_syn.mem <span style='color:#111;'> 3.06KB </span>","children":null,"spread":false},{"title":"memory_busy_wait.mem <span style='color:#111;'> 5.16KB </span>","children":null,"spread":false}],"spread":true},{"title":"cordic","children":[{"title":"vhdl","children":[{"title":"ahb3lite_cordic.vhd <span style='color:#111;'> 9.17KB </span>","children":null,"spread":false},{"title":"Manifest.py <span style='color:#111;'> 39B </span>","children":null,"spread":false}],"spread":false}],"spread":false}],"spread":true}],"spread":true}],"spread":true}]