Verilog的DS18b20代码

上传者: 37579738 | 上传时间: 2019-12-21 20:47:58 | 文件大小: 78KB | 文件类型: zip
Verilog的DS18b20代码,时钟50MHz;

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评论信息

  • vvipalextang :
    是VHDL的,不是verilog,带数码管输出
    2020-10-31

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