FPGA读写 IS61LV25616AL的verilog程序

[{"title":"（ 15 个子文件 57KB ） FPGA读写 IS61LV25616AL的verilog程序","children":[{"title":"SRAM","children":[{"title":"iseconfig","children":[{"title":"SRAM_write.xreport <span style='color:#111;'> 19.96KB </span>","children":null,"spread":false},{"title":"SRAM.xreport <span style='color:#111;'> 19.92KB </span>","children":null,"spread":false},{"title":"cmd.xreport <span style='color:#111;'> 19.89KB </span>","children":null,"spread":false},{"title":"SRAM.projectmgr <span style='color:#111;'> 5.85KB </span>","children":null,"spread":false}],"spread":true},{"title":"cmd_bitgen.xwbt <span style='color:#111;'> 269B </span>","children":null,"spread":false},{"title":"SRAM.gise <span style='color:#111;'> 1.24KB </span>","children":null,"spread":false},{"title":"_xmsgs","children":null,"spread":false},{"title":"SRAM.ucf <span style='color:#111;'> 2.44KB </span>","children":null,"spread":false},{"title":"ipcore_dir","children":null,"spread":false},{"title":"cmd.v <span style='color:#111;'> 1.06KB </span>","children":null,"spread":false},{"title":"SRAM.v <span style='color:#111;'> 2.22KB </span>","children":null,"spread":false},{"title":"SRAM_write_bitgen.xwbt <span style='color:#111;'> 283B </span>","children":null,"spread":false},{"title":"SRAM_write_guide.ncd <span style='color:#111;'> 6.25KB </span>","children":null,"spread":false},{"title":"cmd_guide.ncd <span style='color:#111;'> 39.49KB </span>","children":null,"spread":false},{"title":"SRAM.xise <span style='color:#111;'> 32.98KB </span>","children":null,"spread":false},{"title":"key.v <span style='color:#111;'> 4.21KB </span>","children":null,"spread":false},{"title":"cmd_summary.html <span style='color:#111;'> 3.41KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]