FPGA彩灯控制器代码(vivado)

上传者: 35129057 | 上传时间: 2024-12-25 15:10:34 | 文件大小: 336KB | 文件类型: RAR
考核项目及评分标准 1.基于Verilog语言采用有限状态机设计彩灯控制器,控制LED灯实现预想的演示花型。利用计数器对规定花型演示次数进行计数,同时利用七段数码管线上计数的十进制数。 2.设计内容: (1)功能:设计彩灯控制器,要求控制16个LED灯演示花型一个周期为:从两边往中间逐个亮,全灭;从中间往两头逐个亮,全灭;循环以上行为过程。 (2)一个周期的花型演示完毕后计数器进行计数(0—9),同时用七段数码管线上计数结果。 (3)添加复位按钮,复位后花型演示以及计算功能清零。 (4)采用有限状态机设计,利用vivado自带的仿真软件编写TestBench文件对设计测试。 (5)按要求完成电子版实验报告,需体现设计思路并附上源码。

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