[{"title":"( 2808 个子文件 700.17MB ) 基于FPGA的DDS信号发生器 : DDS_Verilog.rar","children":[{"title":"比特电子视频专用播放器.exe <span style='color:#111;'> 25.14MB </span>","children":null,"spread":false},{"title":"dds.out.sdc.bak <span style='color:#111;'> 3.49KB </span>","children":null,"spread":false},{"title":"triangular.hex <span style='color:#111;'> 973B </span>","children":null,"spread":false},{"title":"triangular_rom.qip <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"pll.qip <span style='color:#111;'> 353B </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]