fpga 串口verilog程序代码

[{"title":"（ 15 个子文件 18KB ） fpga 串口verilog程序代码","children":[{"title":"04_uart_test","children":[{"title":"uart_test.sdc <span style='color:#111;'> 355B </span>","children":null,"spread":false},{"title":"db","children":[{"title":"uart_test.db_info <span style='color:#111;'> 140B </span>","children":null,"spread":false},{"title":"uart_test.pplq.rdb <span style='color:#111;'> 297B </span>","children":null,"spread":false},{"title":"uart_test.sld_design_entry.sci <span style='color:#111;'> 223B </span>","children":null,"spread":false}],"spread":true},{"title":"uart_test.jdi <span style='color:#111;'> 135B </span>","children":null,"spread":false},{"title":"ax301_ax4010_base.tcl <span style='color:#111;'> 683B </span>","children":null,"spread":false},{"title":"uart_test.qsf <span style='color:#111;'> 2.61KB </span>","children":null,"spread":false},{"title":"src","children":[{"title":"uart_rx.v <span style='color:#111;'> 5.87KB </span>","children":null,"spread":false},{"title":"uart_tx.v <span style='color:#111;'> 5.33KB </span>","children":null,"spread":false},{"title":"uart_test.v <span style='color:#111;'> 5.50KB </span>","children":null,"spread":false}],"spread":true},{"title":"uart_test.qpf <span style='color:#111;'> 32B </span>","children":null,"spread":false},{"title":"sim","children":[{"title":"start.do <span style='color:#111;'> 489B </span>","children":null,"spread":false},{"title":"uart_test_tb.v <span style='color:#111;'> 839B </span>","children":null,"spread":false}],"spread":true},{"title":"uart_test.qws <span style='color:#111;'> 728B </span>","children":null,"spread":false},{"title":"uart_test_assignment_defaults.qdf <span style='color:#111;'> 54.32KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]