[{"title":"( 202 个子文件 3.55MB ) 反应计时器设计+毫秒计时器+延时计数器模块(Verilog)","children":[{"title":"counter.v.bak <span style='color:#111;'> 1004B </span>","children":null,"spread":false},{"title":"EDA200532_0402.map.rpt <span style='color:#111;'> 33.37KB </span>","children":null,"spread":false},{"title":"EDA200532_0402.pin <span style='color:#111;'> 19.97KB </span>","children":null,"spread":false},{"title":"Waveform.vwf <span style='color:#111;'> 8.22KB </span>","children":null,"spread":false},{"title":"EDA200532_0402.v.bak <span style='color:#111;'> 775B </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]