上传者: 27595745
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上传时间: 2021-08-21 09:38:05
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文件大小: 128KB
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文件类型: PDF
VHDL Quartus 八进制计数器源代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNTER_8 IS
PORT (
CLK : IN STD_LOGIC;
RS : IN STD_LOGIC;
COUNT_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COUNTER_8;
ARCHITECTURE BEHAVIORAL OF COUNTER_8 IS
SIGNAL NEXT_COUNT : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL D_COUNT : STD_LOGIC_VECTOR(3 DOWNTO 0);