16通道DDR的LVDS接口（VHDL_Verilog_and_doc）.rar

[{"title":"（ 16 个子文件 597KB ） 16通道DDR的LVDS接口（VHDL_Verilog_and_doc）.rar","children":[{"title":"16通道DDR的LVDS接口（VHDL,Verilog and doc）","children":[{"title":"VHDL","children":[{"title":"RESOURCE_SHARING_CONTROL.vhd <span style='color:#111;'> 8.78KB </span>","children":null,"spread":false},{"title":"RT_WINDOW_MONITOR.vhd <span style='color:#111;'> 38.97KB </span>","children":null,"spread":false},{"title":"count_to_16x.vhd <span style='color:#111;'> 2.88KB </span>","children":null,"spread":false},{"title":"seven_bit_reg_w_ce.vhd <span style='color:#111;'> 3.26KB </span>","children":null,"spread":false},{"title":"COUNT_TO_64.vhd <span style='color:#111;'> 3.38KB </span>","children":null,"spread":false},{"title":"count_to_128.vhd <span style='color:#111;'> 3.09KB </span>","children":null,"spread":false},{"title":"DDR_6TO1_16CHAN_RT_RX.vhd <span style='color:#111;'> 97.39KB </span>","children":null,"spread":false},{"title":"DDR_6TO1_16CHAN_RT_TX.vhd <span style='color:#111;'> 21.78KB </span>","children":null,"spread":false},{"title":"BIT_ALIGN_MACHINE.vhd <span style='color:#111;'> 23.06KB </span>","children":null,"spread":false}],"spread":true},{"title":"xapp860.pdf <span style='color:#111;'> 830.92KB </span>","children":null,"spread":false},{"title":"VERILOG","children":[{"title":"RT_WINDOW_MONITOR.v <span style='color:#111;'> 24.17KB </span>","children":null,"spread":false},{"title":"DDR_6TO1_16CHAN_RT_TX.v <span style='color:#111;'> 22.54KB </span>","children":null,"spread":false},{"title":"RESOURCE_SHARING_CONTROL.v <span style='color:#111;'> 5.70KB </span>","children":null,"spread":false},{"title":"DDR_6TO1_16CHAN_RT_RX.v <span style='color:#111;'> 60.22KB </span>","children":null,"spread":false},{"title":"BIT_ALIGN_MACHINE.v <span style='color:#111;'> 14.77KB </span>","children":null,"spread":false}],"spread":true},{"title":"readme.txt <span style='color:#111;'> 4.57KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]