基于verilog的多周期cpu附设计图和流程运行图

[{"title":"（ 73 个子文件 746KB ） 基于verilog的多周期cpu附设计图和流程运行图","children":[{"title":"CPUDZQ","children":[{"title":"mux-2.v.bak <span style='color:#111;'> 435B </span>","children":null,"spread":false},{"title":"CPUDZQ.cr.mti <span style='color:#111;'> 2.29KB </span>","children":null,"spread":false},{"title":"cu.v <span style='color:#111;'> 5.96KB </span>","children":null,"spread":false},{"title":"ALU.v <span style='color:#111;'> 845B </span>","children":null,"spread":false},{"title":"ALU.v.bak <span style='color:#111;'> 851B </span>","children":null,"spread":false},{"title":"GR.v.bak <span style='color:#111;'> 5.60KB </span>","children":null,"spread":false},{"title":"mux4.v.bak <span style='color:#111;'> 687B </span>","children":null,"spread":false},{"title":"vsim.wlf <span style='color:#111;'> 40.00KB </span>","children":null,"spread":false},{"title":"mux4.v <span style='color:#111;'> 541B </span>","children":null,"spread":false},{"title":"CPUDZQ.mpf <span style='color:#111;'> 28.90KB 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style='color:#111;'> 484B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 526B </span>","children":null,"spread":false}],"spread":false},{"title":"@d@z@q@c@p@u","children":[{"title":"verilog.asm <span style='color:#111;'> 23.06KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 469B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 3.61KB </span>","children":null,"spread":false}],"spread":false},{"title":"memory","children":[{"title":"verilog.asm <span style='color:#111;'> 5.69KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 383B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 472B </span>","children":null,"spread":false}],"spread":false},{"title":"register","children":[{"title":"verilog.asm <span style='color:#111;'> 5.36KB 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7.60KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 78B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 1.21KB </span>","children":null,"spread":false}],"spread":false},{"title":"@c@u","children":[{"title":"verilog.asm <span style='color:#111;'> 26.77KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 1.25KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 3.40KB </span>","children":null,"spread":false}],"spread":false},{"title":"_info <span style='color:#111;'> 2.26KB </span>","children":null,"spread":false}],"spread":false},{"title":"mem.v.bak <span style='color:#111;'> 625B </span>","children":null,"spread":false},{"title":"register.v <span style='color:#111;'> 622B </span>","children":null,"spread":false},{"title":"register.v.bak <span style='color:#111;'> 660B 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