[{"title":"( 2 个子文件 3KB ) veriog语言实现UART","children":[{"title":"uart","children":[{"title":"uart_top.v <span style='color:#111;'> 2.52KB </span>","children":null,"spread":false},{"title":"modules.v <span style='color:#111;'> 7.73KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]