[{"title":"( 1114 个子文件 23.64MB ) VERILOG HDL 程序设计实例详解例子","children":[{"title":"transcript <span style='color:#111;'> 2.06KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 908B </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 624B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 9.96KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 496B </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]