方案二.zip_VHDL/FPGA/Verilog_VHDL_源码

上传者: pudn01 | 上传时间: 2021-08-10 10:36:42 | 文件大小: 77KB | 文件类型: ZIP
本系统是基于CPLD和单片机的一种用于信号频率周期、时间间隔和占空比测量的数字频率计,系统由AGC(自动增益控制)电路、宽带放大电路、高速比较电路实现有效值10mV/频率100MHz和处理显示部分组成,其中AGC电路实现幅度自动增益控制使放大后的信号幅度在一定的范围内保持一致,比较电路将前级电路输出的信号转换成CPLD

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