基于verilog HDL 的8051 IP核开发

上传者: pmw_56 | 上传时间: 2023-04-06 15:59:19 | 文件大小: 298KB | 文件类型: ZIP
Verilog HDL (Hardware Description Language) 是一种硬件描述语言,可以在算法级、门级到开关级的多种抽象设计层次上对数字系统建模。它可以描述设计的行为特性、数据流特性、结构组成以及包含响应监控和设计验证方面的时延和波形产生机制。次例程是基于verilog HDL 的8051 IP核开发,很好的学习资料。

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