[{"title":"( 6 个子文件 237KB ) DDR3的控制器(并带有Testbench),可烧录到FPGA中对内存进行读写,相关技术人员可在该代码上修改用于其他场合","children":[{"title":"DDR3 SDRAM Controller","children":[{"title":"~$R3 DRAM controller.docx <span style='color:#111;'> 162B </span>","children":null,"spread":false},{"title":"Title <span style='color:#111;'> 84.89KB </span>","children":null,"spread":false},{"title":"Test HW.jpg <span style='color:#111;'> 64.28KB </span>","children":null,"spread":false},{"title":"DDR3 DRAM controller.docx <span style='color:#111;'> 63.17KB </span>","children":null,"spread":false},{"title":"TestBench.png <span style='color:#111;'> 120.66KB </span>","children":null,"spread":false},{"title":"TestBench <span style='color:#111;'> 84.89KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]