[{"title":"( 64 个子文件 31.41MB ) 最全的verilog-HDL培训教材及参考例程(超多教程和源码)","children":[{"title":"verilog-HDL培训教材及参考例程","children":[{"title":"Verilog 电梯控制器设计 .doc <span style='color:#111;'> 106.00KB </span>","children":null,"spread":false},{"title":"《Verilog HDL数字设计与综合》.pdf <span style='color:#111;'> 1.06MB </span>","children":null,"spread":false},{"title":"关于verilog综合小结.doc <span style='color:#111;'> 27.00KB </span>","children":null,"spread":false},{"title":"Verilog交通灯控制器程序.doc <span style='color:#111;'> 23.00KB </span>","children":null,"spread":false},{"title":"东南大学Verilog讲义","children":[{"title":"4.pdf <span style='color:#111;'> 165.94KB </span>","children":null,"spread":false},{"title":"2.pdf <span style='color:#111;'> 252.29KB </span>","children":null,"spread":false},{"title":"3.pdf <span style='color:#111;'> 51.60KB </span>","children":null,"spread":false},{"title":"1.pdf <span style='color:#111;'> 152.97KB </span>","children":null,"spread":false}],"spread":true},{"title":"Verilog HDL代码描述对状态机综合的研究 .doc <span style='color:#111;'> 74.50KB </span>","children":null,"spread":false},{"title":"卡内基梅陇大学verilog课程讲义 .pdf <span style='color:#111;'> 294.37KB </span>","children":null,"spread":false},{"title":"浙大VerilogHDL","children":[{"title":"浙大vrilogHDL[1].part4.rar <span style='color:#111;'> 1.60MB </span>","children":null,"spread":false},{"title":"v_1.pdf <span style='color:#111;'> 1.88MB </span>","children":null,"spread":false},{"title":"浙大vrilogHDL[1].part3.rar <span style='color:#111;'> 1.90MB </span>","children":null,"spread":false},{"title":"v_5.pdf <span style='color:#111;'> 1.08MB </span>","children":null,"spread":false},{"title":"v_4.pdf <span style='color:#111;'> 1.45MB </span>","children":null,"spread":false},{"title":"浙大vrilogHDL[1].part2.rar <span style='color:#111;'> 1.90MB </span>","children":null,"spread":false},{"title":"浙大vrilogHDL[1].part1.rar <span style='color:#111;'> 1.90MB </span>","children":null,"spread":false},{"title":"v_3.pdf <span style='color:#111;'> 1.31MB </span>","children":null,"spread":false},{"title":"v_2.pdf <span style='color:#111;'> 1.78MB </span>","children":null,"spread":false}],"spread":true},{"title":"Verilog HDL 综合实用教程","children":[{"title":"VerilogHDL 综合实用教程.pdf <span style='color:#111;'> 2.62MB </span>","children":null,"spread":false}],"spread":true},{"title":"VerilogHDL的基础知识.pdf <span style='color:#111;'> 316.61KB </span>","children":null,"spread":false},{"title":"Verilog 脉冲发生器程序.doc <span style='color:#111;'> 22.00KB </span>","children":null,"spread":false},{"title":"Verilog设计代码.rar <span style='color:#111;'> 350.30KB </span>","children":null,"spread":false},{"title":"清华微电子所verilog课件.rar <span style='color:#111;'> 110.82KB </span>","children":null,"spread":false},{"title":"华为:Verilog HDL入门教程.pdf <span style='color:#111;'> 280.97KB </span>","children":null,"spread":false},{"title":"Verilog语言练习与讲解(中文).pdf <span style='color:#111;'> 432.87KB </span>","children":null,"spread":false},{"title":"Verilog数字系统设计示例.rar <span style='color:#111;'> 41.25KB </span>","children":null,"spread":false},{"title":"Verilog实例","children":[{"title":"计数器.v <span style='color:#111;'> 2.80KB </span>","children":null,"spread":false},{"title":"双向脚(clocked bidirectional pin).txt <span style='color:#111;'> 626B </span>","children":null,"spread":false},{"title":"用状态机设计的交通灯控制器.v <span style='color:#111;'> 2.36KB </span>","children":null,"spread":false},{"title":"一个简单的状态机.v <span style='color:#111;'> 577B </span>","children":null,"spread":false},{"title":"带load,clr等功能的寄存器.v <span style='color:#111;'> 1.25KB </span>","children":null,"spread":false},{"title":"元件例化与层次设计.txt <span style='color:#111;'> 942B </span>","children":null,"spread":false},{"title":"一个同步状态机.txt <span style='color:#111;'> 1.48KB </span>","children":null,"spread":false},{"title":"锁存器.v <span style='color:#111;'> 229B </span>","children":null,"spread":false},{"title":"12位寄存器.v <span style='color:#111;'> 224B </span>","children":null,"spread":false},{"title":"相应加法器的测试向量(test bench).v <span style='color:#111;'> 440B </span>","children":null,"spread":false},{"title":"Verilog HDL 实例说明.doc <span style='color:#111;'> 19.50KB </span>","children":null,"spread":false}],"spread":false},{"title":"Verilog黄金参考指南.pdf <span style='color:#111;'> 511.67KB </span>","children":null,"spread":false},{"title":"Verilog语言练习与讲解(中文补充).pdf <span style='color:#111;'> 114.08KB </span>","children":null,"spread":false},{"title":"Verilog 非阻塞赋值的仿真综合问题.doc <span style='color:#111;'> 132.00KB </span>","children":null,"spread":false},{"title":"Verilog HDL硬件描述语言(a verilog HDL primer 译本)(美)J.Bhasher著 徐振林等译","children":[{"title":"004.PDF <span style='color:#111;'> 289.30KB </span>","children":null,"spread":false},{"title":"012.PDF <span style='color:#111;'> 567.80KB </span>","children":null,"spread":false},{"title":"006.PDF <span style='color:#111;'> 137.08KB </span>","children":null,"spread":false},{"title":"009.PDF <span style='color:#111;'> 225.16KB </span>","children":null,"spread":false},{"title":"011.PDF <span style='color:#111;'> 472.12KB </span>","children":null,"spread":false},{"title":"内容简介.TXT <span style='color:#111;'> 330B </span>","children":null,"spread":false},{"title":"010.PDF <span style='color:#111;'> 696.73KB </span>","children":null,"spread":false},{"title":"005.PDF <span style='color:#111;'> 314.69KB </span>","children":null,"spread":false},{"title":"013.PDF <span style='color:#111;'> 735.78KB </span>","children":null,"spread":false},{"title":"003.PDF <span style='color:#111;'> 362.63KB </span>","children":null,"spread":false},{"title":"001.PDF <span style='color:#111;'> 85.68KB </span>","children":null,"spread":false},{"title":"007.PDF <span style='color:#111;'> 143.86KB </span>","children":null,"spread":false},{"title":"目录.TXT <span style='color:#111;'> 4.20KB </span>","children":null,"spread":false},{"title":"002.PDF <span style='color:#111;'> 298.26KB </span>","children":null,"spread":false},{"title":"008.PDF <span style='color:#111;'> 623.68KB </span>","children":null,"spread":false}],"spread":false},{"title":"Verilog Golden Reference Guide.pdf <span style='color:#111;'> 270.43KB </span>","children":null,"spread":false},{"title":"硬件描述语言Verilog(第四版).pdf <span style='color:#111;'> 5.45MB </span>","children":null,"spread":false},{"title":"SDRAM控制器软核的Verilog设计.doc <span style='color:#111;'> 187.50KB </span>","children":null,"spread":false},{"title":"verilog的阻塞和非阻塞赋值.doc <span style='color:#111;'> 80.00KB </span>","children":null,"spread":false},{"title":"SPI串行总线接口的Verilog实现 .doc <span style='color:#111;'> 54.50KB </span>","children":null,"spread":false},{"title":"可综合的Verilog语法(剑桥大学,影印).pdf <span style='color:#111;'> 412.39KB </span>","children":null,"spread":false},{"title":"Verilog的键盘源码keypad—有去抖功能.doc <span style='color:#111;'> 28.50KB </span>","children":null,"spread":false},{"title":"Verilog hdl教程135个经典设计实例(王金明).rar <span style='color:#111;'> 191.15KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]