[{"title":"( 6 个子文件 5KB ) 串口 uart verilog FPGA","children":[{"title":"uart_module","children":[{"title":"uart_top.v.bak <span style='color:#111;'> 1.66KB </span>","children":null,"spread":false},{"title":"uart_rx.v <span style='color:#111;'> 2.50KB </span>","children":null,"spread":false},{"title":"uart_tx.v <span style='color:#111;'> 3.05KB </span>","children":null,"spread":false},{"title":"uart_top.v <span style='color:#111;'> 1.68KB </span>","children":null,"spread":false},{"title":"uart_top(0).v <span style='color:#111;'> 1.33KB </span>","children":null,"spread":false},{"title":"uart_tx.v.bak <span style='color:#111;'> 3.06KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]