verilog实现的带FIFO的UART模块

[{"title":"（ 530 个子文件 975KB ） verilog实现的带FIFO的UART模块","children":[{"title":"cbx_args.txt <span style='color:#111;'> 279B </span>","children":null,"spread":false},{"title":"fsl2serial.asm.rpt <span style='color:#111;'> 6.48KB </span>","children":null,"spread":false},{"title":"fifo.v <span style='color:#111;'> 1.91KB </span>","children":null,"spread":false},{"title":"serial.v.bak <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"serial_in.v <span style='color:#111;'> 4.89KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]