UART verilog仿真实现

[{"title":"（ 5 个子文件 3KB ） UART verilog仿真实现","children":[{"title":"UART","children":[{"title":"uarttx.v <span style='color:#111;'> 2.11KB </span>","children":null,"spread":false},{"title":"uartrx.v <span style='color:#111;'> 2.32KB </span>","children":null,"spread":false},{"title":"uartrxtx.vwf <span style='color:#111;'> 11.13KB </span>","children":null,"spread":false},{"title":"clkdiv.v <span style='color:#111;'> 389B </span>","children":null,"spread":false},{"title":"testuart.v <span style='color:#111;'> 352B </span>","children":null,"spread":false}],"spread":true}],"spread":true}]