ddr_verilog

上传者: may_cuc2008 | 上传时间: 2021-09-03 11:54:59 | 文件大小: 735KB | 文件类型: RAR
ddr控制器的程序,用verilog语言实现,带有仿真文件,可以直接使用,保证正确

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资源详情

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</span>","children":null,"spread":false},{"title":"ddr_sdram_rm.tcl <span style='color:#111;'> 979B </span>","children":null,"spread":false},{"title":"ddr_sdram.srm <span style='color:#111;'> 458.93KB </span>","children":null,"spread":false},{"title":"ddr_sdram.xrf <span style='color:#111;'> 112.41KB </span>","children":null,"spread":false},{"title":"ddr_sdram.prj <span style='color:#111;'> 1.15KB </span>","children":null,"spread":false},{"title":"ddr_sdram.tlg <span style='color:#111;'> 3.50KB </span>","children":null,"spread":false},{"title":"ddr_sdram.tcl <span style='color:#111;'> 455B </span>","children":null,"spread":false},{"title":"ddr_data_path.srr <span style='color:#111;'> 62.96KB </span>","children":null,"spread":false},{"title":"ddr_data_path.srs <span style='color:#111;'> 28.71KB </span>","children":null,"spread":false},{"title":"ddr_data_path.srm <span style='color:#111;'> 459.19KB </span>","children":null,"spread":false},{"title":"ddr_sdram.vqm <span style='color:#111;'> 581.37KB </span>","children":null,"spread":false},{"title":"ddr_sdram.srr <span style='color:#111;'> 73.41KB </span>","children":null,"spread":false},{"title":"ddr_sdram.sdc <span style='color:#111;'> 428B </span>","children":null,"spread":false},{"title":"ddr_data_path.tlg <span style='color:#111;'> 3.50KB </span>","children":null,"spread":false},{"title":"ddr_data_path.xrf <span style='color:#111;'> 112.90KB </span>","children":null,"spread":false},{"title":"ddr_sdram_cons.tcl <span style='color:#111;'> 194B </span>","children":null,"spread":false}],"spread":false}],"spread":true},{"title":"www.pudn.com.txt <span style='color:#111;'> 218B </span>","children":null,"spread":false},{"title":"doc","children":[{"title":"ddr_sdram.pdf <span style='color:#111;'> 461.72KB </span>","children":null,"spread":false}],"spread":true},{"title":"simulation","children":[{"title":"work","children":[{"title":"ddr_data_path","children":[{"title":"verilog.psm <span style='color:#111;'> 23.52KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 817B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 3.14KB </span>","children":null,"spread":false}],"spread":true},{"title":"altclklock","children":[{"title":"verilog.psm <span style='color:#111;'> 20.19KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 899B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 2.28KB </span>","children":null,"spread":false}],"spread":true},{"title":"ddr_sdram_tb","children":[{"title":"verilog.psm <span style='color:#111;'> 60.30KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 102B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 9.18KB </span>","children":null,"spread":false}],"spread":true},{"title":"pll1","children":[{"title":"verilog.psm <span style='color:#111;'> 4.78KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 256B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 823B </span>","children":null,"spread":false}],"spread":true},{"title":"_info <span style='color:#111;'> 1.08KB </span>","children":null,"spread":false},{"title":"ddr_command","children":[{"title":"verilog.psm <span style='color:#111;'> 45.15KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 1.30KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 5.01KB </span>","children":null,"spread":false}],"spread":true},{"title":"ddr_sdram","children":[{"title":"verilog.psm <span style='color:#111;'> 27.97KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 1.06KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 4.45KB </span>","children":null,"spread":false}],"spread":true},{"title":"ddr_control_interface","children":[{"title":"verilog.psm <span style='color:#111;'> 21.21KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 1.09KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 2.72KB </span>","children":null,"spread":false}],"spread":false},{"title":"mt46v4m16","children":[{"title":"verilog.psm <span style='color:#111;'> 226.59KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 1.15KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 24.52KB </span>","children":null,"spread":false}],"spread":false}],"spread":true},{"title":"ddr_compile_all.v <span style='color:#111;'> 213B </span>","children":null,"spread":false},{"title":"modelsim.ini <span style='color:#111;'> 7.55KB </span>","children":null,"spread":false},{"title":"ddr_sdram_tb.v <span style='color:#111;'> 17.93KB </span>","children":null,"spread":false},{"title":"readme.txt <span style='color:#111;'> 377B </span>","children":null,"spread":false}],"spread":true},{"title":"source","children":[{"title":"altclklock.v <span style='color:#111;'> 9.06KB </span>","children":null,"spread":false},{"title":"pll1.v <span style='color:#111;'> 4.54KB </span>","children":null,"spread":false},{"title":"ddr_control_interface.v <span style='color:#111;'> 9.20KB </span>","children":null,"spread":false},{"title":"Params.v <span style='color:#111;'> 1.02KB </span>","children":null,"spread":false},{"title":"ddr_Command.v <span style='color:#111;'> 16.20KB </span>","children":null,"spread":false},{"title":"ddr_sdram.v <span style='color:#111;'> 8.86KB </span>","children":null,"spread":false},{"title":"ddr_data_path.v <span style='color:#111;'> 9.22KB </span>","children":null,"spread":false}],"spread":true},{"title":"readme.txt <span style='color:#111;'> 563B </span>","children":null,"spread":false}],"spread":true}]

评论信息

  • w347451201 :
    有点贵,资源确实不错
    2020-10-13
  • qq_41553378 :
    看不懂太难了
    2019-06-29
  • neogeo64 :
    不错,可以用的。
    2017-09-04
  • lz_15219600 :
    这是一个DDR存储器的例程,我想要的是DDR双沿触发原语的例程,理解错误
    2016-03-31
  • jessie9940509 :
    谢谢分享,正在学习DDR2.希望能有帮助.刚刚看过,不错的资源.推荐.
    2015-09-26

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