ddr_verilog

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style='color:#111;'> 581.37KB </span>","children":null,"spread":false},{"title":"ddr_sdram.srr <span style='color:#111;'> 73.41KB </span>","children":null,"spread":false},{"title":"ddr_sdram.sdc <span style='color:#111;'> 428B </span>","children":null,"spread":false},{"title":"ddr_data_path.tlg <span style='color:#111;'> 3.50KB </span>","children":null,"spread":false},{"title":"ddr_data_path.xrf <span style='color:#111;'> 112.90KB </span>","children":null,"spread":false},{"title":"ddr_sdram_cons.tcl <span style='color:#111;'> 194B </span>","children":null,"spread":false}],"spread":false}],"spread":true},{"title":"www.pudn.com.txt <span style='color:#111;'> 218B </span>","children":null,"spread":false},{"title":"doc","children":[{"title":"ddr_sdram.pdf <span style='color:#111;'> 461.72KB </span>","children":null,"spread":false}],"spread":true},{"title":"simulation","children":[{"title":"work","children":[{"title":"ddr_data_path","children":[{"title":"verilog.psm <span style='color:#111;'> 23.52KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 817B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 3.14KB </span>","children":null,"spread":false}],"spread":true},{"title":"altclklock","children":[{"title":"verilog.psm <span style='color:#111;'> 20.19KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 899B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 2.28KB </span>","children":null,"spread":false}],"spread":true},{"title":"ddr_sdram_tb","children":[{"title":"verilog.psm <span style='color:#111;'> 60.30KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 102B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 9.18KB </span>","children":null,"spread":false}],"spread":true},{"title":"pll1","children":[{"title":"verilog.psm <span style='color:#111;'> 4.78KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 256B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 823B </span>","children":null,"spread":false}],"spread":true},{"title":"_info <span style='color:#111;'> 1.08KB </span>","children":null,"spread":false},{"title":"ddr_command","children":[{"title":"verilog.psm <span style='color:#111;'> 45.15KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 1.30KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 5.01KB </span>","children":null,"spread":false}],"spread":true},{"title":"ddr_sdram","children":[{"title":"verilog.psm <span style='color:#111;'> 27.97KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 1.06KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 4.45KB </span>","children":null,"spread":false}],"spread":true},{"title":"ddr_control_interface","children":[{"title":"verilog.psm <span style='color:#111;'> 21.21KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 1.09KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 2.72KB </span>","children":null,"spread":false}],"spread":false},{"title":"mt46v4m16","children":[{"title":"verilog.psm <span style='color:#111;'> 226.59KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 1.15KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 24.52KB </span>","children":null,"spread":false}],"spread":false}],"spread":true},{"title":"ddr_compile_all.v <span style='color:#111;'> 213B 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<span style='color:#111;'> 9.22KB </span>","children":null,"spread":false}],"spread":true},{"title":"readme.txt <span style='color:#111;'> 563B </span>","children":null,"spread":false}],"spread":true}]