[{"title":"( 6 个子文件 8.44MB ) EDA技术与Verilog HDL","children":[{"title":"第6章 Verilog HDL设计进阶.ppt <span style='color:#111;'> 2.02MB </span>","children":null,"spread":false},{"title":"第2章 EDA设计流程及其工具.ppt <span style='color:#111;'> 238.50KB </span>","children":null,"spread":false},{"title":"第4章 Verilog HDL设计初步.ppt <span style='color:#111;'> 1.16MB </span>","children":null,"spread":false},{"title":"第1章 概述.ppt <span style='color:#111;'> 172.00KB </span>","children":null,"spread":false},{"title":"第3章 FPGA CPLD结构与应用.ppt <span style='color:#111;'> 1.31MB </span>","children":null,"spread":false},{"title":"第5章 Quartus II应用初步.ppt <span style='color:#111;'> 4.46MB </span>","children":null,"spread":false}],"spread":true}]