基于FPGA的电子时钟设计clock1

[{"title":"（ 235 个子文件 6.57MB ） 基于FPGA的电子时钟设计clock1","children":[{"title":"_info <span style='color:#111;'> 13.12KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 8.37KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 7.28KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 6.00KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 5.20KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 3.13KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 2.75KB </span>","children":null,"spread":false},{"title":"_opt__lock <span style='color:#111;'> 35B </span>","children":null,"spread":false},{"title":"_vmake <span style='color:#111;'> 29B </span>","children":null,"spread":false},{"title":"_vmake <span style='color:#111;'> 29B </span>","children":null,"spread":false},{"title":"_vmake <span style='color:#111;'> 29B </span>","children":null,"spread":false},{"title":"_vmake <span style='color:#111;'> 29B </span>","children":null,"spread":false},{"title":"_vmake <span style='color:#111;'> 29B </span>","children":null,"spread":false},{"title":"_vmake <span style='color:#111;'> 29B </span>","children":null,"spread":false},{"title":"_vmake <span style='color:#111;'> 29B </span>","children":null,"spread":false},{"title":"clock_1.root_partition.cmp.ammdb <span style='color:#111;'> 561B </span>","children":null,"spread":false},{"title":"clock_1.vpr.ammdb <span style='color:#111;'> 523B </span>","children":null,"spread":false},{"title":"clock_1.map.ammdb <span style='color:#111;'> 138B </span>","children":null,"spread":false},{"title":"clock.v.bak <span style='color:#111;'> 2.36KB </span>","children":null,"spread":false},{"title":"clock_1_run_msim_rtl_verilog.do.bak <span style='color:#111;'> 1.91KB </span>","children":null,"spread":false},{"title":"top.v.bak <span style='color:#111;'> 1.90KB </span>","children":null,"spread":false},{"title":"clk_1hz.v.bak <span style='color:#111;'> 780B </span>","children":null,"spread":false},{"title":"clock_1_run_msim_rtl_verilog.do.bak1 <span style='color:#111;'> 1.91KB </span>","children":null,"spread":false},{"title":"clock_1_run_msim_rtl_verilog.do.bak2 <span style='color:#111;'> 1.90KB </span>","children":null,"spread":false},{"title":"clock_1.cmp.bpm <span style='color:#111;'> 705B </span>","children":null,"spread":false},{"title":"clock_1.map.bpm <span style='color:#111;'> 674B </span>","children":null,"spread":false},{"title":"clock_1.cmp.cdb <span style='color:#111;'> 49.77KB </span>","children":null,"spread":false},{"title":"clock_1.root_partition.cmp.cdb <span style='color:#111;'> 21.49KB </span>","children":null,"spread":false},{"title":"clock_1.sgdiff.cdb <span style='color:#111;'> 15.98KB </span>","children":null,"spread":false},{"title":"clock_1.map.cdb <span style='color:#111;'> 15.00KB </span>","children":null,"spread":false},{"title":"clock_1.root_partition.map.cdb <span style='color:#111;'> 14.59KB </span>","children":null,"spread":false},{"title":"clock_1.rtlv_sg.cdb <span style='color:#111;'> 10.69KB </span>","children":null,"spread":false},{"title":"clock_1.(7).cnf.cdb <span style='color:#111;'> 6.75KB </span>","children":null,"spread":false},{"title":"clock_1.(15).cnf.cdb <span style='color:#111;'> 5.90KB </span>","children":null,"spread":false},{"title":"clock_1.(2).cnf.cdb <span style='color:#111;'> 5.46KB </span>","children":null,"spread":false},{"title":"clock_1.(3).cnf.cdb <span style='color:#111;'> 4.72KB </span>","children":null,"spread":false},{"title":"clock_1.(1).cnf.cdb <span style='color:#111;'> 2.23KB </span>","children":null,"spread":false},{"title":"clock_1.(0).cnf.cdb <span style='color:#111;'> 1.83KB </span>","children":null,"spread":false},{"title":"clock_1.map_bb.cdb <span style='color:#111;'> 1.77KB </span>","children":null,"spread":false},{"title":"clock_1.root_partition.map.hbdb.cdb <span style='color:#111;'> 1.27KB </span>","children":null,"spread":false},{"title":"clock_1.(6).cnf.cdb <span style='color:#111;'> 1.22KB </span>","children":null,"spread":false},{"title":"clock_1.(14).cnf.cdb <span style='color:#111;'> 1.18KB </span>","children":null,"spread":false},{"title":"clock_1.(10).cnf.cdb <span style='color:#111;'> 1.16KB </span>","children":null,"spread":false},{"title":"clock_1.(9).cnf.cdb <span style='color:#111;'> 1.15KB </span>","children":null,"spread":false},{"title":"clock_1.(4).cnf.cdb <span style='color:#111;'> 1.15KB </span>","children":null,"spread":false},{"title":"clock_1.(16).cnf.cdb <span style='color:#111;'> 1.14KB </span>","children":null,"spread":false},{"title":"clock_1.(12).cnf.cdb <span style='color:#111;'> 1.13KB </span>","children":null,"spread":false},{"title":"clock_1.(11).cnf.cdb <span style='color:#111;'> 1.07KB </span>","children":null,"spread":false},{"title":"clock_1.(5).cnf.cdb <span style='color:#111;'> 1.06KB </span>","children":null,"spread":false},{"title":"clock_1.(13).cnf.cdb <span style='color:#111;'> 1.04KB </span>","children":null,"spread":false},{"title":"clock_1.(17).cnf.cdb <span style='color:#111;'> 1.04KB </span>","children":null,"spread":false},{"title":"clock_1.rtlv_sg_swap.cdb <span style='color:#111;'> 1.03KB </span>","children":null,"spread":false},{"title":"clock_1.(8).cnf.cdb <span style='color:#111;'> 933B </span>","children":null,"spread":false},{"title":"clock_1.root_partition.map.reg_db.cdb <span style='color:#111;'> 363B </span>","children":null,"spread":false},{"title":"clock_1.cdf <span style='color:#111;'> 350B </span>","children":null,"spread":false},{"title":"Chain1.cdf <span style='color:#111;'> 335B </span>","children":null,"spread":false},{"title":"logic_util_heursitic.dat <span style='color:#111;'> 18.00KB </span>","children":null,"spread":false},{"title":"clock_1.db_info <span style='color:#111;'> 155B </span>","children":null,"spread":false},{"title":"clock_1.db_info <span style='color:#111;'> 155B </span>","children":null,"spread":false},{"title":"clock_1.tiscmp.slow_1200mv_0c.ddb <span style='color:#111;'> 215.05KB </span>","children":null,"spread":false},{"title":"clock_1.tiscmp.slow_1200mv_85c.ddb <span style='color:#111;'> 214.89KB </span>","children":null,"spread":false},{"title":"clock_1.tiscmp.fast_1200mv_0c.ddb <span style='color:#111;'> 214.10KB </span>","children":null,"spread":false},{"title":"clock_1.tiscmp.fastest_slow_1200mv_0c.ddb <span style='color:#111;'> 125.93KB </span>","children":null,"spread":false},{"title":"clock_1.tiscmp.fastest_slow_1200mv_85c.ddb <span style='color:#111;'> 125.76KB </span>","children":null,"spread":false},{"title":"clock_1.asm_labs.ddb <span style='color:#111;'> 10.96KB </span>","children":null,"spread":false},{"title":"clock_1.tis_db_list.ddb <span style='color:#111;'> 250B </span>","children":null,"spread":false},{"title":"clock_1.pti_db_list.ddb <span style='color:#111;'> 192B </span>","children":null,"spread":false},{"title":"clock_1.root_partition.cmp.dfp <span style='color:#111;'> 33B </span>","children":null,"spread":false},{"title":"clock_1_run_msim_rtl_verilog.do <span style='color:#111;'> 1.90KB </span>","children":null,"spread":false},{"title":"clock_1.done <span style='color:#111;'> 26B </span>","children":null,"spread":false},{"title":"clock_1.root_partition.map.dpi <span style='color:#111;'> 964B </span>","children":null,"spread":false},{"title":"clock_1.root_partition.map.hbdb.hb_info <span style='color:#111;'> 46B </span>","children":null,"spread":false},{"title":"clock_1.sgdiff.hdb <span style='color:#111;'> 26.78KB </span>","children":null,"spread":false},{"title":"clock_1.cmp.hdb <span style='color:#111;'> 21.35KB </span>","children":null,"spread":false},{"title":"clock_1.root_partition.cmp.hdb <span style='color:#111;'> 20.93KB </span>","children":null,"spread":false},{"title":"clock_1.root_partition.map.hdb <span style='color:#111;'> 20.84KB </span>","children":null,"spread":false},{"title":"clock_1.map.hdb <span style='color:#111;'> 20.58KB </span>","children":null,"spread":false},{"title":"clock_1.root_partition.map.hbdb.hdb <span style='color:#111;'> 20.23KB </span>","children":null,"spread":false},{"title":"clock_1.pre_map.hdb <span style='color:#111;'> 13.50KB </span>","children":null,"spread":false},{"title":"clock_1.rtlv.hdb <span style='color:#111;'> 13.35KB </span>","children":null,"spread":false},{"title":"clock_1.map_bb.hdb <span style='color:#111;'> 12.20KB </span>","children":null,"spread":false},{"title":"clock_1.(7).cnf.hdb <span style='color:#111;'> 3.48KB </span>","children":null,"spread":false},{"title":"clock_1.(15).cnf.hdb <span style='color:#111;'> 2.95KB </span>","children":null,"spread":false},{"title":"clock_1.(3).cnf.hdb <span style='color:#111;'> 1.76KB </span>","children":null,"spread":false},{"title":"clock_1.(2).cnf.hdb <span style='color:#111;'> 1.61KB </span>","children":null,"spread":false},{"title":"clock_1.(1).cnf.hdb <span style='color:#111;'> 1.23KB </span>","children":null,"spread":false},{"title":"clock_1.(0).cnf.hdb <span style='color:#111;'> 1.09KB </span>","children":null,"spread":false},{"title":"clock_1.(6).cnf.hdb <span style='color:#111;'> 793B </span>","children":null,"spread":false},{"title":"clock_1.(14).cnf.hdb <span style='color:#111;'> 772B </span>","children":null,"spread":false},{"title":"clock_1.(9).cnf.hdb <span style='color:#111;'> 680B </span>","children":null,"spread":false},{"title":"clock_1.(8).cnf.hdb <span style='color:#111;'> 657B </span>","children":null,"spread":false},{"title":"clock_1.(11).cnf.hdb <span style='color:#111;'> 654B </span>","children":null,"spread":false},{"title":"clock_1.(17).cnf.hdb <span style='color:#111;'> 654B </span>","children":null,"spread":false},{"title":"clock_1.(5).cnf.hdb <span style='color:#111;'> 654B </span>","children":null,"spread":false},{"title":"clock_1.(13).cnf.hdb <span style='color:#111;'> 653B </span>","children":null,"spread":false},{"title":"clock_1.(12).cnf.hdb <span style='color:#111;'> 607B </span>","children":null,"spread":false},{"title":"clock_1.(4).cnf.hdb <span style='color:#111;'> 605B </span>","children":null,"spread":false},{"title":"clock_1.(16).cnf.hdb <span style='color:#111;'> 603B </span>","children":null,"spread":false},{"title":"clock_1.(10).cnf.hdb <span style='color:#111;'> 602B </span>","children":null,"spread":false},{"title":"clock_1.hier_info <span style='color:#111;'> 6.78KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]