[{"title":"( 52 个子文件 93KB ) 3-Verilog HDL时钟激励设计.7z","children":[{"title":"3-Verilog HDL时钟激励设计","children":[{"title":"vivado","children":[{"title":"3_design_top","children":[{"title":"design_top","children":[{"title":"design_top.srcs","children":[{"title":"sources_1","children":[{"title":"new","children":[{"title":"clock_top.v <span style='color:#111;'> 833B </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true},{"title":"design_top.ip_user_files","children":[{"title":"README.txt <span style='color:#111;'> 130B </span>","children":null,"spread":false}],"spread":true},{"title":"design_top.sim","children":[{"title":"sim_1","children":[{"title":"behav","children":[{"title":"xsim","children":[{"title":"webtalk_18284.backup.jou <span style='color:#111;'> 998B </span>","children":null,"spread":false},{"title":"glbl.v <span style='color:#111;'> 1.44KB </span>","children":null,"spread":false},{"title":"elaborate.log <span style='color:#111;'> 715B </span>","children":null,"spread":false},{"title":"compile.bat <span style='color:#111;'> 836B </span>","children":null,"spread":false},{"title":"clock_top_vlog.prj <span style='color:#111;'> 237B </span>","children":null,"spread":false},{"title":"webtalk_18284.backup.log <span style='color:#111;'> 1.53KB </span>","children":null,"spread":false},{"title":"simulate.log <span style='color:#111;'> 50B </span>","children":null,"spread":false},{"title":"elaborate.bat <span style='color:#111;'> 1.13KB </span>","children":null,"spread":false},{"title":"xsim.ini <span style='color:#111;'> 40B </span>","children":null,"spread":false},{"title":"simulate.bat <span style='color:#111;'> 918B </span>","children":null,"spread":false},{"title":"xelab.pb <span style='color:#111;'> 1.41KB </span>","children":null,"spread":false},{"title":"xvlog.log <span style='color:#111;'> 218B </span>","children":null,"spread":false},{"title":"clock_top_behav.wdb <span style='color:#111;'> 9.78KB </span>","children":null,"spread":false},{"title":"webtalk.jou <span style='color:#111;'> 998B </span>","children":null,"spread":false},{"title":"xvlog.pb <span style='color:#111;'> 376B </span>","children":null,"spread":false},{"title":"webtalk.log <span style='color:#111;'> 1.15KB </span>","children":null,"spread":false},{"title":"clock_top.tcl <span style='color:#111;'> 460B </span>","children":null,"spread":false},{"title":".Xil","children":[{"title":"Webtalk-18284-XA-TSDN034","children":[{"title":"webtalk","children":null,"spread":false}],"spread":false},{"title":"Webtalk-16924-XA-TSDN034","children":[{"title":"webtalk","children":null,"spread":false}],"spread":false}],"spread":false},{"title":"xsim.dir","children":[{"title":"xil_defaultlib","children":[{"title":"glbl.sdb <span style='color:#111;'> 3.64KB </span>","children":null,"spread":false},{"title":"clock_top.sdb <span style='color:#111;'> 1.66KB </span>","children":null,"spread":false},{"title":"xil_defaultlib.rlx <span style='color:#111;'> 304B </span>","children":null,"spread":false}],"spread":false},{"title":"clock_top_behav","children":[{"title":"xsimSettings.ini <span style='color:#111;'> 1.41KB </span>","children":null,"spread":false},{"title":"xsim.xdbg <span style='color:#111;'> 696B </span>","children":null,"spread":false},{"title":"xsim.rtti <span style='color:#111;'> 190B </span>","children":null,"spread":false},{"title":"xsimkernel.log <span style='color:#111;'> 326B </span>","children":null,"spread":false},{"title":"Compile_Options.txt <span style='color:#111;'> 252B </span>","children":null,"spread":false},{"title":"xsimk.exe <span style='color:#111;'> 64.24KB </span>","children":null,"spread":false},{"title":"xsim.dbg <span style='color:#111;'> 5.38KB </span>","children":null,"spread":false},{"title":"xsim.reloc <span style='color:#111;'> 905B </span>","children":null,"spread":false},{"title":"TempBreakPointFile.txt <span style='color:#111;'> 29B </span>","children":null,"spread":false},{"title":"xsim.rlx <span style='color:#111;'> 806B </span>","children":null,"spread":false},{"title":"xsimcrash.log <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"xsim.type <span style='color:#111;'> 24B </span>","children":null,"spread":false},{"title":"webtalk","children":[{"title":".xsim_webtallk.info <span style='color:#111;'> 64B </span>","children":null,"spread":false},{"title":"usage_statistics_ext_xsim.html <span style='color:#111;'> 3.20KB </span>","children":null,"spread":false},{"title":"usage_statistics_ext_xsim.wdm <span style='color:#111;'> 1.09KB </span>","children":null,"spread":false},{"title":"usage_statistics_ext_xsim.xml <span style='color:#111;'> 2.77KB </span>","children":null,"spread":false},{"title":"xsim_webtalk.tcl <span style='color:#111;'> 3.71KB </span>","children":null,"spread":false}],"spread":false},{"title":"xsim.svtype <span style='color:#111;'> 39B </span>","children":null,"spread":false},{"title":"obj","children":[{"title":"xsim_1.win64.obj <span style='color:#111;'> 2.83KB </span>","children":null,"spread":false},{"title":"xsim_0.win64.obj <span style='color:#111;'> 4.82KB </span>","children":null,"spread":false},{"title":"xsim_1.c <span style='color:#111;'> 4.49KB </span>","children":null,"spread":false}],"spread":false},{"title":"xsim.mem <span style='color:#111;'> 2.72KB </span>","children":null,"spread":false}],"spread":false}],"spread":false}],"spread":false}],"spread":true}],"spread":true}],"spread":true},{"title":"design_top.cache","children":[{"title":"wt","children":[{"title":"gui_handlers.wdf <span style='color:#111;'> 2.76KB </span>","children":null,"spread":false},{"title":"webtalk_pa.xml <span style='color:#111;'> 3.27KB </span>","children":null,"spread":false},{"title":"project.wpc <span style='color:#111;'> 61B </span>","children":null,"spread":false},{"title":"java_command_handlers.wdf <span style='color:#111;'> 508B </span>","children":null,"spread":false},{"title":"xsim.wdf <span style='color:#111;'> 239B </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"design_top.hw","children":[{"title":"design_top.lpr <span style='color:#111;'> 290B </span>","children":null,"spread":false}],"spread":true},{"title":"design_top.xpr <span style='color:#111;'> 10.21KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true},{"title":"fpga","children":[{"title":"3-Verilog HDL时钟激励设计.pdf <span style='color:#111;'> 82.24KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}]