基于I2C编写的I2C_MASTER和I2C_SLAVE在一个模块的verilog代码

[{"title":"（ 8 个子文件 8KB ） 基于I2C编写的I2C_MASTER和I2C_SLAVE在一个模块的verilog代码","children":[{"title":"i2c","children":[{"title":"i2c.v <span style='color:#111;'> 23.96KB </span>","children":null,"spread":false},{"title":"delay.v <span style='color:#111;'> 408B </span>","children":null,"spread":false},{"title":"i2c_reg.v <span style='color:#111;'> 2.19KB </span>","children":null,"spread":false},{"title":"i2c_top.v <span style='color:#111;'> 2.92KB </span>","children":null,"spread":false},{"title":"deglitch.v <span style='color:#111;'> 1.05KB </span>","children":null,"spread":false},{"title":"wb2reg.v <span style='color:#111;'> 3.07KB </span>","children":null,"spread":false},{"title":"i2c_defines.v <span style='color:#111;'> 214B </span>","children":null,"spread":false},{"title":"reg.v <span style='color:#111;'> 339B </span>","children":null,"spread":false}],"spread":true}],"spread":true}]