简易逻辑分析仪的verilog代码

[{"title":"（ 102 个子文件 650KB ） 简易逻辑分析仪的verilog代码","children":[{"title":"luojiyi_demo.qsf <span style='color:#111;'> 5.00KB </span>","children":null,"spread":false},{"title":"dpram256x12.vhd <span style='color:#111;'> 9.33KB </span>","children":null,"spread":false},{"title":"dpram256x12_bb.v <span style='color:#111;'> 7.60KB </span>","children":null,"spread":false},{"title":"luojiyi_demo.tan.rpt <span style='color:#111;'> 76.52KB </span>","children":null,"spread":false},{"title":"luojiyi_demo.asm.rpt <span style='color:#111;'> 9.24KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]