xilinx中值滤波程序vhdl源码 median filter

上传者: liywf | 上传时间: 2021-05-31 12:57:20 | 文件大小: 525KB | 文件类型: ZIP
FPGA应用。VHDL语言实现图像处理中的种植滤波

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[{"title":"( 43 个子文件 525KB ) xilinx中值滤波程序vhdl源码 median filter","children":[{"title":"rank2d_latency.vhd <span style='color:#111;'> 6.54KB </span>","children":null,"spread":false},{"title":"fvg_y.vhd <span style='color:#111;'> 9.17KB </span>","children":null,"spread":false},{"title":"fvg_sum.vhd <span style='color:#111;'> 4.56KB </span>","children":null,"spread":false},{"title":"sub_inst.vhd <span style='color:#111;'> 5.30KB </span>","children":null,"spread":false},{"title":"sub_module.vhd <span style='color:#111;'> 1.21KB </span>","children":null,"spread":false},{"title":"cntr1_old.vhd <span style='color:#111;'> 5.25KB </span>","children":null,"spread":false},{"title":"cntr1_new.vhd <span style='color:#111;'> 5.24KB </span>","children":null,"spread":false},{"title":"filter_core.vhd <span style='color:#111;'> 22.82KB </span>","children":null,"spread":false},{"title":"testbench","children":[{"title":"test_images","children":[{"title":"testpic_1s.bmp <span style='color:#111;'> 23.49KB </span>","children":null,"spread":false},{"title":"sw_1.bmp <span style='color:#111;'> 653.96KB </span>","children":null,"spread":false},{"title":"pattern_s.bmp <span style='color:#111;'> 23.49KB </span>","children":null,"spread":false},{"title":"pcb_sp.bmp <span style='color:#111;'> 77.15KB </span>","children":null,"spread":false},{"title":"pattern2_s.bmp <span style='color:#111;'> 23.49KB </span>","children":null,"spread":false},{"title":"pattern_s3.bmp <span style='color:#111;'> 5.99KB </span>","children":null,"spread":false},{"title":"s.bmp <span style='color:#111;'> 12.05KB </span>","children":null,"spread":false},{"title":"checked_50x40.bmp <span style='color:#111;'> 5.99KB </span>","children":null,"spread":false},{"title":"pattern_s2.bmp <span style='color:#111;'> 5.99KB </span>","children":null,"spread":false},{"title":"testpic_1sm.bmp <span style='color:#111;'> 23.49KB </span>","children":null,"spread":false},{"title":"testpic_1.bmp <span style='color:#111;'> 351.62KB </span>","children":null,"spread":false}],"spread":false},{"title":"test_top.vhd <span style='color:#111;'> 4.10KB </span>","children":null,"spread":false},{"title":"matlab","children":[{"title":"sysgen","children":[{"title":"rank2d_top_config.m <span style='color:#111;'> 6.61KB </span>","children":null,"spread":false},{"title":"rank2d_postproc.m <span style='color:#111;'> 1.54KB </span>","children":null,"spread":false},{"title":"rank_2d.mdl <span style='color:#111;'> 88.69KB </span>","children":null,"spread":false},{"title":"rank2d_golden.m <span style='color:#111;'> 1016B </span>","children":null,"spread":false},{"title":"rank2d_init_mdl.m <span style='color:#111;'> 3.66KB </span>","children":null,"spread":false},{"title":"tb_2drank_sysgen_rst.do <span style='color:#111;'> 4.85KB </span>","children":null,"spread":false},{"title":"padd2d.m <span style='color:#111;'> 997B </span>","children":null,"spread":false}],"spread":true},{"title":"rank1D_golden.m <span style='color:#111;'> 493B </span>","children":null,"spread":false},{"title":"saltpepper_add.m <span style='color:#111;'> 781B </span>","children":null,"spread":false},{"title":"rank1D.m <span style='color:#111;'> 817B </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"fvg_yuv.vhd <span style='color:#111;'> 3.40KB </span>","children":null,"spread":false},{"title":"rank2d_top.vhd <span style='color:#111;'> 32.60KB </span>","children":null,"spread":false},{"title":"GenXlib_utils.vhd <span style='color:#111;'> 7.34KB </span>","children":null,"spread":false},{"title":"lbuff_mem.vhd <span style='color:#111;'> 4.45KB </span>","children":null,"spread":false},{"title":"comp_module.vhd <span style='color:#111;'> 3.52KB </span>","children":null,"spread":false},{"title":"delay_line_srl32.vhd <span style='color:#111;'> 5.02KB </span>","children":null,"spread":false},{"title":"delay_line.vhd <span style='color:#111;'> 4.85KB </span>","children":null,"spread":false},{"title":"delay_line_srl16.vhd <span style='color:#111;'> 4.94KB </span>","children":null,"spread":false},{"title":"GenXlib_arch.vhd <span style='color:#111;'> 18.16KB </span>","children":null,"spread":false},{"title":"rank2d_utils.vhd <span style='color:#111;'> 10.09KB </span>","children":null,"spread":false},{"title":"readme.txt <span style='color:#111;'> 4.09KB </span>","children":null,"spread":false},{"title":"sub_inst_v2.vhd <span style='color:#111;'> 5.12KB </span>","children":null,"spread":false},{"title":"sub_inst_v4.vhd <span style='color:#111;'> 4.88KB </span>","children":null,"spread":false}],"spread":true}]

评论信息

  • haohaoyes :
    确实可以用,不过没什么注释,编程的思想逻辑挺好,比较容易理清。
    2015-11-17
  • zdyyongjing :
    能不能搞点注释呢
    2015-06-16
  • XD_0535 :
    确实不错可以用
    2012-09-04

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