基于verilog语言的8位CPU设计

[{"title":"（ 127 个子文件 494KB ） 基于verilog语言的8位CPU设计","children":[{"title":"KD_CPU.xst <span style='color:#111;'> 1.10KB </span>","children":null,"spread":false},{"title":"PC.v <span style='color:#111;'> 950B </span>","children":null,"spread":false},{"title":"KD_CPU.v <span style='color:#111;'> 7.81KB </span>","children":null,"spread":false},{"title":"counter.v <span style='color:#111;'> 1.11KB </span>","children":null,"spread":false},{"title":"multiply.v <span style='color:#111;'> 1.31KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]