dds数字移相信号发生器

[{"title":"（ 97 个子文件 375KB ） dds数字移相信号发生器","children":[{"title":"DDS_VHDL.qws <span style='color:#111;'> 2.25KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.qpf <span style='color:#111;'> 910B </span>","children":null,"spread":false},{"title":"DDS_VHDL.sof <span style='color:#111;'> 137.21KB </span>","children":null,"spread":false},{"title":"ADDER32B.vhd <span style='color:#111;'> 344B </span>","children":null,"spread":false},{"title":"sin_rom.vhd <span style='color:#111;'> 6.02KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.fit.summary <span style='color:#111;'> 416B </span>","children":null,"spread":false},{"title":"DDS_VHDL.vhd <span style='color:#111;'> 2.56KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.tan.summary <span style='color:#111;'> 1.64KB </span>","children":null,"spread":false},{"title":"sin_rom_wave0.jpg <span style='color:#111;'> 104.33KB </span>","children":null,"spread":false},{"title":"sin_rom_waveforms.html <span style='color:#111;'> 1.04KB </span>","children":null,"spread":false},{"title":"LUT10X10.MIF <span style='color:#111;'> 11.83KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.bsf <span style='color:#111;'> 2.14KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.fit.rpt <span style='color:#111;'> 108.07KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.dpf <span style='color:#111;'> 239B </span>","children":null,"spread":false},{"title":"DDS_VHDL.fit.smsg <span style='color:#111;'> 411B </span>","children":null,"spread":false},{"title":"ADDER32B.vhd.bak <span style='color:#111;'> 334B </span>","children":null,"spread":false},{"title":"DDS_VHDL.map.rpt <span style='color:#111;'> 40.11KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.map.summary <span style='color:#111;'> 322B </span>","children":null,"spread":false},{"title":"DDS_VHDL.done <span style='color:#111;'> 26B </span>","children":null,"spread":false},{"title":"db","children":[{"title":"DDS_VHDL.map.bpm <span style='color:#111;'> 624B </span>","children":null,"spread":false},{"title":"DDS_VHDL.cmp.logdb <span style='color:#111;'> 4B </span>","children":null,"spread":false},{"title":"DDS_VHDL.(4).cnf.hdb <span style='color:#111;'> 597B </span>","children":null,"spread":false},{"title":"DDS_VHDL.sgdiff.hdb <span style='color:#111;'> 13.70KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.psp <span style='color:#111;'> 3B </span>","children":null,"spread":false},{"title":"DDS_VHDL.map_bb.logdb <span style='color:#111;'> 4B </span>","children":null,"spread":false},{"title":"DDS_VHDL.rtlv_sg.cdb <span style='color:#111;'> 9.24KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.sld_design_entry.sci <span style='color:#111;'> 154B </span>","children":null,"spread":false},{"title":"DDS_VHDL.cmp.cdb <span style='color:#111;'> 13.85KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.(4).cnf.cdb <span style='color:#111;'> 1.22KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.(1).cnf.cdb <span style='color:#111;'> 940B </span>","children":null,"spread":false},{"title":"DDS_VHDL.(3).cnf.hdb <span style='color:#111;'> 963B </span>","children":null,"spread":false},{"title":"DDS_VHDL.(2).cnf.cdb <span style='color:#111;'> 1.10KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.(6).cnf.hdb <span style='color:#111;'> 624B </span>","children":null,"spread":false},{"title":"DDS_VHDL.(2).cnf.hdb <span style='color:#111;'> 608B </span>","children":null,"spread":false},{"title":"DDS_VHDL.map.hdb <span style='color:#111;'> 10.75KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.cmp_bb.cdb <span style='color:#111;'> 7.01KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.pre_map.cdb <span style='color:#111;'> 5.88KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.map.logdb <span style='color:#111;'> 4B </span>","children":null,"spread":false},{"title":"DDS_VHDL.sgdiff.cdb <span style='color:#111;'> 3.98KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.(1).cnf.hdb <span style='color:#111;'> 579B </span>","children":null,"spread":false},{"title":"DDS_VHDL.db_info <span style='color:#111;'> 137B </span>","children":null,"spread":false},{"title":"DDS_VHDL.(0).cnf.hdb <span style='color:#111;'> 766B </span>","children":null,"spread":false},{"title":"DDS_VHDL.cmp.hdb <span style='color:#111;'> 11.28KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.eco.cdb <span style='color:#111;'> 161B </span>","children":null,"spread":false},{"title":"DDS_VHDL.syn_hier_info <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"DDS_VHDL.pss <span style='color:#111;'> 679B </span>","children":null,"spread":false},{"title":"DDS_VHDL.map.qmsg <span style='color:#111;'> 1.74KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.cmp.rdb <span style='color:#111;'> 24.13KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.tan.qmsg <span style='color:#111;'> 32.41KB </span>","children":null,"spread":false},{"title":"prev_cmp_DDS_VHDL.fit.qmsg <span style='color:#111;'> 29.23KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.(0).cnf.cdb <span style='color:#111;'> 1.54KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.cbx.xml <span style='color:#111;'> 342B </span>","children":null,"spread":false},{"title":"DDS_VHDL.pre_map.hdb <span style='color:#111;'> 13.12KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.(7).cnf.cdb <span style='color:#111;'> 3.28KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.cmp0.ddb <span style='color:#111;'> 27.71KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.dbp <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"DDS_VHDL.(5).cnf.hdb <span style='color:#111;'> 706B </span>","children":null,"spread":false},{"title":"DDS_VHDL.fit.qmsg <span style='color:#111;'> 38.69KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.map.ecobp <span style='color:#111;'> 28B </span>","children":null,"spread":false},{"title":"DDS_VHDL.cmp_bb.logdb <span style='color:#111;'> 4B </span>","children":null,"spread":false},{"title":"DDS_VHDL.rtlv.hdb <span style='color:#111;'> 13.09KB </span>","children":null,"spread":false},{"title":"altsyncram_u631.tdf <span style='color:#111;'> 9.69KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.map.cdb <span style='color:#111;'> 5.12KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.(3).cnf.cdb <span style='color:#111;'> 1.91KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.map_bb.hdb <span style='color:#111;'> 10.75KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.cmp.ecobp <span style='color:#111;'> 28B </span>","children":null,"spread":false},{"title":"prev_cmp_DDS_VHDL.tan.qmsg <span style='color:#111;'> 33.73KB </span>","children":null,"spread":false},{"title":"prev_cmp_DDS_VHDL.map.qmsg <span style='color:#111;'> 6.47KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.rtlv_sg_swap.cdb <span style='color:#111;'> 2.70KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.(7).cnf.hdb <span style='color:#111;'> 1.09KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.cmp_bb.hdb <span style='color:#111;'> 10.95KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.cmp.bpm <span style='color:#111;'> 646B </span>","children":null,"spread":false},{"title":"DDS_VHDL.asm.qmsg <span style='color:#111;'> 1.80KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.hier_info <span style='color:#111;'> 24.44KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.signalprobe.cdb <span style='color:#111;'> 427B </span>","children":null,"spread":false},{"title":"DDS_VHDL.cmp.tdb <span style='color:#111;'> 17.31KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.cmp_bb.rcf <span style='color:#111;'> 3.90KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.(6).cnf.cdb <span style='color:#111;'> 2.24KB </span>","children":null,"spread":false},{"title":"prev_cmp_DDS_VHDL.asm.qmsg <span style='color:#111;'> 1.80KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.map_bb.cdb <span style='color:#111;'> 4.77KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.sld_design_entry_dsc.sci <span style='color:#111;'> 154B </span>","children":null,"spread":false},{"title":"DDS_VHDL.(5).cnf.cdb <span style='color:#111;'> 1.22KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.hif <span style='color:#111;'> 8.22KB </span>","children":null,"spread":false}],"spread":false},{"title":"DDS_VHDL.flow.rpt <span style='color:#111;'> 4.16KB </span>","children":null,"spread":false},{"title":"sin_rom.inc <span style='color:#111;'> 874B </span>","children":null,"spread":false},{"title":"greybox_tmp","children":null,"spread":false},{"title":"DDS_VHDL.tan.rpt <span style='color:#111;'> 116.79KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.pin <span style='color:#111;'> 29.69KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.qsf <span style='color:#111;'> 2.70KB </span>","children":null,"spread":false},{"title":"DDS_VHDL.vhd.bak <span style='color:#111;'> 2.56KB </span>","children":null,"spread":false},{"title":"sin_rom_inst.vhd <span style='color:#111;'> 107B </span>","children":null,"spread":false},{"title":"DDS_VHDL.pof <span style='color:#111;'> 512.18KB </span>","children":null,"spread":false},{"title":"REG32B.vhd <span style='color:#111;'> 388B </span>","children":null,"spread":false},{"title":"REG10B.vhd <span style='color:#111;'> 386B </span>","children":null,"spread":false},{"title":"ADDER10B.vhd <span style='color:#111;'> 341B </span>","children":null,"spread":false},{"title":"sin_rom.cmp <span style='color:#111;'> 965B </span>","children":null,"spread":false},{"title":"DDS_VHDL.asm.rpt <span style='color:#111;'> 6.93KB </span>","children":null,"spread":false},{"title":"prev_cmp_DDS_VHDL.qmsg <span style='color:#111;'> 89.75KB </span>","children":null,"spread":false}],"spread":true}]