FPGA写的同步FIFO

[{"title":"（ 53 个子文件 239KB ） FPGA写的同步FIFO","children":[{"title":"调试好的同步fifo modlesim","children":[{"title":"testbench","children":[{"title":"wave.doc <span style='color:#111;'> 159.50KB </span>","children":null,"spread":false},{"title":"altsyncram.v <span style='color:#111;'> 3.76KB </span>","children":null,"spread":false},{"title":"fifo.v <span style='color:#111;'> 4.10KB </span>","children":null,"spread":false},{"title":"ram128x.v <span style='color:#111;'> 9.48KB </span>","children":null,"spread":false},{"title":"fifo_tb.v.bak <span style='color:#111;'> 1.54KB </span>","children":null,"spread":false},{"title":"proj","children":[{"title":"fifo.map.summary <span style='color:#111;'> 611B </span>","children":null,"spread":false},{"title":"fifo_nativelink_simulation.rpt <span style='color:#111;'> 957B </span>","children":null,"spread":false},{"title":"fifo.qpf <span style='color:#111;'> 1.24KB </span>","children":null,"spread":false},{"title":"fifo.qsf <span style='color:#111;'> 3.18KB </span>","children":null,"spread":false},{"title":"fifo.done <span style='color:#111;'> 26B </span>","children":null,"spread":false},{"title":"fifo.map.rpt <span style='color:#111;'> 39.14KB </span>","children":null,"spread":false},{"title":"fifo.flow.rpt <span style='color:#111;'> 6.23KB </span>","children":null,"spread":false}],"spread":true},{"title":"fifo_tb.v <span style='color:#111;'> 1.55KB </span>","children":null,"spread":false},{"title":"~$wave.doc <span style='color:#111;'> 162B </span>","children":null,"spread":false},{"title":"fifo.v.bak <span style='color:#111;'> 4.09KB </span>","children":null,"spread":false},{"title":"ram128x.qip <span style='color:#111;'> 282B </span>","children":null,"spread":false},{"title":"ram128x_bb.v <span style='color:#111;'> 7.79KB </span>","children":null,"spread":false},{"title":"fifo 网上没验证过的.v <span style='color:#111;'> 1.15KB </span>","children":null,"spread":false}],"spread":false},{"title":"sim","children":[{"title":"fifo_tb_user.do <span style='color:#111;'> 486B </span>","children":null,"spread":false},{"title":"wlftniz1ff <span style='color:#111;'> 16.00KB </span>","children":null,"spread":false},{"title":"wlftgrmxds <span style='color:#111;'> 16.00KB </span>","children":null,"spread":false},{"title":"nco_vo_transcript <span style='color:#111;'> 123.25KB </span>","children":null,"spread":false},{"title":"wlftftj2i1 <span style='color:#111;'> 16.00KB </span>","children":null,"spread":false},{"title":"vsim.wlf <span style='color:#111;'> 40.00KB </span>","children":null,"spread":false},{"title":"rtl_work","children":[{"title":"ram128x","children":[{"title":"_primary.dbs <span style='color:#111;'> 2.25KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 15.62KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 471B </span>","children":null,"spread":false},{"title":"verilog.rw <span style='color:#111;'> 7.38KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 1.98KB </span>","children":null,"spread":false}],"spread":true},{"title":"fifo","children":[{"title":"_primary.dbs <span style='color:#111;'> 5.16KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 28.23KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 716B </span>","children":null,"spread":false},{"title":"verilog.rw <span style='color:#111;'> 5.75KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 1.86KB </span>","children":null,"spread":false}],"spread":true},{"title":"altsyncram","children":[{"title":"_primary.dbs <span style='color:#111;'> 3.40KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 27.31KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 3.38KB </span>","children":null,"spread":false},{"title":"verilog.rw <span style='color:#111;'> 11.89KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 2.35KB </span>","children":null,"spread":false}],"spread":true},{"title":"_vmake <span style='color:#111;'> 26B </span>","children":null,"spread":false},{"title":"fifo_tb","children":[{"title":"_primary.dbs <span style='color:#111;'> 3.11KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 12.26KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 74B </span>","children":null,"spread":false},{"title":"verilog.rw <span style='color:#111;'> 4.39KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 1.19KB </span>","children":null,"spread":false}],"spread":true},{"title":"_temp","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 1.05KB </span>","children":null,"spread":false}],"spread":true},{"title":"wlftn5ehx0 <span style='color:#111;'> 40.00KB </span>","children":null,"spread":false},{"title":"wlft760sk8 <span style='color:#111;'> 16.00KB </span>","children":null,"spread":false},{"title":"fifo_tb.do <span style='color:#111;'> 7.88KB </span>","children":null,"spread":false},{"title":"fifo_tb.do.bak <span style='color:#111;'> 7.85KB </span>","children":null,"spread":false},{"title":"modelsim.ini <span style='color:#111;'> 53.85KB </span>","children":null,"spread":false},{"title":"wlftae53kj <span style='color:#111;'> 40.00KB </span>","children":null,"spread":false},{"title":"fifo_tb_user.do.bak <span style='color:#111;'> 368B </span>","children":null,"spread":false}],"spread":false}],"spread":true}],"spread":true}]