verilog写的8位加法器

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style='color:#111;'> 1.27KB </span>","children":null,"spread":false}],"spread":true},{"title":"adder8","children":[{"title":"_primary.dat <span style='color:#111;'> 635B </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 360B </span>","children":null,"spread":false},{"title":"verilog.rw <span style='color:#111;'> 2.96KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 7.49KB </span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'> 1.47KB </span>","children":null,"spread":false}],"spread":true},{"title":"adder1","children":[{"title":"_primary.dat <span style='color:#111;'> 188B </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 303B </span>","children":null,"spread":false},{"title":"verilog.rw <span style='color:#111;'> 1.15KB </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 3.30KB 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<span style='color:#111;'> 1.66KB </span>","children":null,"spread":false},{"title":"voptntjyxa <span style='color:#111;'> 1.18KB </span>","children":null,"spread":false}],"spread":false},{"title":"_info <span style='color:#111;'> 1.06KB </span>","children":null,"spread":false}],"spread":true},{"title":"tb_adder8.v.bak <span style='color:#111;'> 565B </span>","children":null,"spread":false},{"title":"adder1.v.bak <span style='color:#111;'> 110B </span>","children":null,"spread":false},{"title":"adder8.cr.mti <span style='color:#111;'> 959B </span>","children":null,"spread":false},{"title":"vsim.wlf <span style='color:#111;'> 1.20MB </span>","children":null,"spread":false},{"title":"adder8.v.bak <span style='color:#111;'> 368B </span>","children":null,"spread":false},{"title":"adder8.mpf <span style='color:#111;'> 54.97KB </span>","children":null,"spread":false},{"title":"adder4.v.bak <span style='color:#111;'> 292B </span>","children":null,"spread":false}],"spread":true}]