串口通信实现（verilog带testbench文件）

fpga开发

uart_tx模块由单脉冲信号send_go使能，将data[7:0]读入uart_tx模块，发送完成后，输出单脉冲tx_done。总之完成了一个串口发送模块。可以参考我的文章https://blog.csdn.net/lgk1996/article/details/124523461?spm=1001.2014.3001.5502 环境：vivado + verilog

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