[{"title":"( 68 个子文件 572KB ) FPGA开发例程","children":[{"title":"cy4BoardTest","children":[{"title":"cy4.qsf <span style='color:#111;'> 8.96KB </span>","children":null,"spread":false},{"title":"ip_core","children":[{"title":"pll","children":[{"title":"greybox_tmp","children":[{"title":"cbx_args.txt <span style='color:#111;'> 1.66KB </span>","children":null,"spread":false}],"spread":true},{"title":"pll_controller.v <span style='color:#111;'> 19.11KB </span>","children":null,"spread":false},{"title":"pll_controller_bb.v <span style='color:#111;'> 14.62KB </span>","children":null,"spread":false},{"title":"pll_controller.qip <span style='color:#111;'> 480B </span>","children":null,"spread":false},{"title":"pll_controller.ppf <span style='color:#111;'> 696B </span>","children":null,"spread":false},{"title":"pll_controller_inst.v <span style='color:#111;'> 192B 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style='color:#111;'> 3.59KB </span>","children":null,"spread":false},{"title":"test_timing.v <span style='color:#111;'> 4.14KB </span>","children":null,"spread":false},{"title":"rtc_top.v <span style='color:#111;'> 2.79KB </span>","children":null,"spread":false},{"title":"iic_controller.v <span style='color:#111;'> 6.43KB </span>","children":null,"spread":false},{"title":"seg7.v <span style='color:#111;'> 3.10KB </span>","children":null,"spread":false},{"title":"key_check.v <span style='color:#111;'> 2.39KB </span>","children":null,"spread":false},{"title":"sram_controller.v <span style='color:#111;'> 4.31KB </span>","children":null,"spread":false},{"title":"led_controller.v <span style='color:#111;'> 1.32KB </span>","children":null,"spread":false},{"title":"beep.v <span style='color:#111;'> 1.12KB </span>","children":null,"spread":false},{"title":"speed_setting.v <span style='color:#111;'> 1.84KB </span>","children":null,"spread":false},{"title":"lcd_controller.v <span style='color:#111;'> 9.12KB </span>","children":null,"spread":false},{"title":"cy4.v <span style='color:#111;'> 11.65KB </span>","children":null,"spread":false},{"title":"adc_controller.v <span style='color:#111;'> 3.41KB </span>","children":null,"spread":false},{"title":"rom_init.mif <span style='color:#111;'> 12.51KB </span>","children":null,"spread":false},{"title":"dac_controller.v <span style='color:#111;'> 4.40KB </span>","children":null,"spread":false},{"title":"para_define.v <span style='color:#111;'> 477B </span>","children":null,"spread":false},{"title":"rtc_controller.v <span style='color:#111;'> 6.24KB </span>","children":null,"spread":false},{"title":"my_uart_tx.v <span style='color:#111;'> 1.96KB </span>","children":null,"spread":false}],"spread":false},{"title":"simulation","children":[{"title":"modelsim","children":[{"title":"cy4_v.sdo <span style='color:#111;'> 724.02KB </span>","children":null,"spread":false},{"title":"cy4_min_1200mv_0c_fast.vo <span style='color:#111;'> 1.13MB </span>","children":null,"spread":false},{"title":"cy4_8_1200mv_0c_slow.vo <span style='color:#111;'> 1.13MB </span>","children":null,"spread":false},{"title":"cy4_8_1200mv_0c_v_slow.sdo <span style='color:#111;'> 723.37KB </span>","children":null,"spread":false},{"title":"cy4_modelsim.xrf <span style='color:#111;'> 137.72KB </span>","children":null,"spread":false},{"title":"cy4.sft <span style='color:#111;'> 323B </span>","children":null,"spread":false},{"title":"cy4_8_1200mv_85c_v_slow.sdo <span style='color:#111;'> 724.02KB </span>","children":null,"spread":false},{"title":"cy4_8_1200mv_85c_slow.vo <span style='color:#111;'> 1.13MB </span>","children":null,"spread":false},{"title":"cy4_min_1200mv_0c_v_fast.sdo <span style='color:#111;'> 705.40KB </span>","children":null,"spread":false},{"title":"cy4.vo <span style='color:#111;'> 1.13MB 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