一套cache的Verilog HDL代码

[{"title":"（ 25 个子文件 30KB ） 一套cache的Verilog HDL代码","children":[{"title":"DPC.v","children":[{"title":"cacheblockLE <span style='color:#111;'> 15.79KB </span>","children":null,"spread":false},{"title":"single Memory Decoder Module <span style='color:#111;'> 2.09KB </span>","children":null,"spread":false},{"title":"DPC.v <span style='color:#111;'> 20.14KB </span>","children":null,"spread":false},{"title":"DPC <span style='color:#111;'> 20.14KB </span>","children":null,"spread":false},{"title":"single Memory Decoder Module.v.bak <span style='color:#111;'> 2.09KB </span>","children":null,"spread":false},{"title":"single Memory write Module <span style='color:#111;'> 2.51KB </span>","children":null,"spread":false},{"title":"Hierarchical Buffered Switch.v <span style='color:#111;'> 1.30KB </span>","children":null,"spread":false},{"title":"single Context Logical Element Unit.v.bak <span style='color:#111;'> 1.89KB </span>","children":null,"spread":false},{"title":"Hierarchical Buffered Switch <span style='color:#111;'> 1.30KB </span>","children":null,"spread":false},{"title":"Logical Element Unit.v.bak <span style='color:#111;'> 5.63KB </span>","children":null,"spread":false},{"title":"Cache Block LE.v <span style='color:#111;'> 14.52KB </span>","children":null,"spread":false},{"title":"logicalelement <span style='color:#111;'> 5.63KB </span>","children":null,"spread":false},{"title":"Cache Block.v.bak <span style='color:#111;'> 1.68KB </span>","children":null,"spread":false},{"title":"single Memory write Module.v <span style='color:#111;'> 2.50KB </span>","children":null,"spread":false},{"title":"Hierarchical Buffered Switch.v.bak <span style='color:#111;'> 1.30KB </span>","children":null,"spread":false},{"title":"switch box.v <span style='color:#111;'> 2.48KB </span>","children":null,"spread":false},{"title":"switch box.v.bak <span style='color:#111;'> 2.48KB </span>","children":null,"spread":false},{"title":"Cache Block.v <span style='color:#111;'> 1.98KB </span>","children":null,"spread":false},{"title":"cacheblock <span style='color:#111;'> 1.68KB </span>","children":null,"spread":false},{"title":"Logical Element Unit.v <span style='color:#111;'> 5.63KB </span>","children":null,"spread":false},{"title":"switchbox <span style='color:#111;'> 2.48KB </span>","children":null,"spread":false},{"title":"single Memory write Module.v.bak <span style='color:#111;'> 2.51KB </span>","children":null,"spread":false},{"title":"Cache Block LE.v.bak <span style='color:#111;'> 17.33KB </span>","children":null,"spread":false},{"title":"single Memory Decoder Module.v <span style='color:#111;'> 2.09KB </span>","children":null,"spread":false},{"title":"single Context Logical Element Unit.v <span style='color:#111;'> 1.89KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]