基于verilog的数字钟实现

[{"title":"（ 579 个子文件 1.67MB ） 基于verilog的数字钟实现","children":[{"title":"min.v.bak <span style='color:#111;'> 477B </span>","children":null,"spread":false},{"title":"clock.asm.rpt <span style='color:#111;'> 6.88KB </span>","children":null,"spread":false},{"title":"decore.qsf <span style='color:#111;'> 2.56KB </span>","children":null,"spread":false},{"title":"clock.fit.rpt <span style='color:#111;'> 170.29KB </span>","children":null,"spread":false},{"title":"decore.fit.summary <span style='color:#111;'> 410B </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]