MT53E256M16D1规格书 MT53E256M16D1

LPDDR4/LPDDR4X SDRAM MT53E256M16D1, MT53E256M32D2 Features This data sheet is for LPDDR4 and LPDDR4X unified product based on LPDDR4X information. Refer to LPDDR4 setting section LPDDR4 1.10V V DDQ at the end of this data sheet. • Ultra-low-voltage core and I/O power supplies – V DD1 = 1.70–1.95V; 1.80V nominal – V DD2 = 1.06–1.17V; 1.10V nominal – V DDQ = 1.06–1.17V; 1.10V nominal or Low V DDQ = 0.57–0.65V; 0.60V nominal • Frequency range – 1866–10 MHz (data rate range: 3733–20 Mbps/ pin) • 16n prefetch DDR architecture • 8 internal banks per channel for concurrent opera- tion • Single-data-rate CMD/ADR entry • Bidirectional/differential data strobe per byte lane • Programmable READ and WRITE latencies (RL/WL) • Programmable and on-the-fly burst lengths (BL = 16, 32) • Directed per-bank refresh for concurrent bank op- eration and ease of command scheduling • Up to 8.5 GB/s per die • On-chip temperature sensor to control self refresh rate • Partial-array self refresh (PASR) • Selectable output drive strength (DS) • Clock-stop capability • RoHS-compliant, “green” packaging • Programmable V SS (ODT) termination Options Marking • V DD1 /V DD2 /V DDQ : 1.80V/1.10V/1.10V or 0.60V E • Array configuration – 256 Meg × 16 (1 channel ×16 I/O) 256M16 1 – 256 Meg × 32 (2 channels ×16 I/O) 256M32 • Device configuration – 256M16 × 1 die in package D1 – 256M16 × 2 die in package D2 • FBGA “green” package – 200-ball WFBGA (10mm × 14.5mm × 0.8mm, Ø0.35 SMD) DS • Speed grade, cycle time – 535ps @ RL = 32/36 -053 – 468ps @ RL = 36/40 -046 • Operating temperature range – –25°C to +85°C WT • Revision :B Note: 1. MT53E256M16D1 is Preliminary status, with the following legal disclaimer: Products and specifications discussed herein are for evalu- ation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet speci- fications.