设计一个通用寄存器组,16位的寄存器。(含报告)

上传者: jj070728 | 上传时间: 2019-12-21 20:00:40 | 文件大小: 525KB | 文件类型: rar
设计一个通用寄存器组,满足以下要求: ①通用寄存器组中有4个16位的寄存器。 ②当复位信号reset=0时,将通用寄存器组中的4个寄存器清零。 ③通用寄存器组中有1个写入端口,当DRWr=1时,在时钟clk的上升沿将数据总线上的数据写入DR[1..0]指定的寄存器。 ④通用寄存器组中有两个读出端口,由控制信IDC控制,分别对应算术逻辑单元的A口和B口。IDC=0选择目的操作数;IDC=1选择源操作数。 ⑤设计要求层次设计。底层的设计实体有3个:通用寄存器组数据输入模块包括4个16位寄存器,具有复位功能和允许写功能;一个4选1多路开关,负责选择寄存器的读出。一个2路数据分配器实现数据双端口输出,顶层设计构成一个完整的通用寄存器组。

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评论信息

  • 干了这碗老陈醋 :
    这个sel的选择作用怎么体现的啊,没有看懂啊……
    2020-05-30
  • kopstand :
    实用!很有帮助
    2016-01-24
  • stayEmpty :
    真的很不错啊,帮了我的大忙
    2015-10-18
  • marcia_tang :
    挺不错的,很实用
    2014-04-09
  • bulletnoid :
    很好的参考,很好懂
    2013-11-20

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