Microprocessor Architecture - From Simple Pipelines to Chip Multiprocessors

上传者: hychieftain | 上传时间: 2019-12-21 19:55:56 | 文件大小: 12.5MB | 文件类型: pdf
作者: Jean-Loup Baer 出版社: Cambridge University Press 出版年: 2009-12-7 页数: 382 定价: USD 90.00 装帧: Hardcover ISBN: 9780521769921 This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as: * The policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorder buffers * Optimizations for high performance such as branch predictors, instruction scheduling, and load-store speculations * Design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors * State-of-the-art multithreading and multiprocessing emphasizing single chip implementations Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity.

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评论信息

  • Feynmann :
    cache 一章讲的挺好的
    2019-05-30
  • enoch :
    先只看了目录,是别人推荐看的。绝对值得学习!谢谢!
    2018-09-29
  • NWPUDAYE :
    很有用,顺便学习英语
    2018-07-19

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