[{"title":"( 5 个子文件 3.6MB ) vscode的Verilog插件.zip","children":[{"title":"GitHub.github-vscode-theme-6.0.0.vsix <span style='color:#111;'> 81.74KB </span>","children":null,"spread":false},{"title":"mshr-h.VerilogHDL-1.5.4.vsix <span style='color:#111;'> 3.43MB </span>","children":null,"spread":false},{"title":"bmpenuelas.waveform-render-0.19.0.vsix <span style='color:#111;'> 143.09KB </span>","children":null,"spread":false},{"title":"MS-CEINTL.vscode-language-pack-zh-hans-1.68.6150916.vsix <span style='color:#111;'> 352.15KB </span>","children":null,"spread":false},{"title":"Gtylcara-Gewinn.verilog-0.1.5.vsix <span style='color:#111;'> 7.05KB </span>","children":null,"spread":false}],"spread":true}]