36个Verilog设计基础代码移位寄存器编码器加法减法器分频器计数器逻辑源码Quartus工程文件合集.zip

[{"title":"（ 2340 个子文件 5.26MB ） 36个Verilog设计基础代码移位寄存器编码器加法减法器分频器计数器逻辑源码Quartus工程文件合集.zip","children":[{"title":"cnt_jf.vwf <span style='color:#111;'> 3.74KB </span>","children":null,"spread":false},{"title":"cnt_jf.done <span style='color:#111;'> 26B </span>","children":null,"spread":false},{"title":"cnt_jf.v <span style='color:#111;'> 1005B </span>","children":null,"spread":false},{"title":"cnt_jf.map.rpt <span style='color:#111;'> 21.26KB </span>","children":null,"spread":false},{"title":"cnt_jf.smart_action.txt <span style='color:#111;'> 5B </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]