基于FPGA的sd卡控制器

[{"title":"（ 57 个子文件 1.96MB ） 基于FPGA的sd卡控制器","children":[{"title":"sdr_ctrl","children":[{"title":"tags","children":null,"spread":false},{"title":"branches","children":null,"spread":false},{"title":"trunk","children":[{"title":"models","children":null,"spread":false},{"title":"verif","children":[{"title":"dump","children":[{"title":"SDR-32Bit-Read-Transaction.jpg <span style='color:#111;'> 170.65KB </span>","children":null,"spread":false},{"title":"Application-ReadRequest.jpg <span style='color:#111;'> 112.57KB </span>","children":null,"spread":false},{"title":"SDR-16Bit-Read-Transaction.jpg <span style='color:#111;'> 177.08KB </span>","children":null,"spread":false},{"title":"SDR-32Bit-Write-Transaction.jpg <span style='color:#111;'> 173.27KB </span>","children":null,"spread":false},{"title":"Application-WriteRequest.jpg <span style='color:#111;'> 119.71KB </span>","children":null,"spread":false},{"title":"SDR-16Bit-Write-Transaction.jpg <span style='color:#111;'> 196.99KB </span>","children":null,"spread":false}],"spread":true},{"title":"log","children":[{"title":"top_sdr32_sim.log <span style='color:#111;'> 426.43KB </span>","children":null,"spread":false},{"title":"top_SDR_16BIT_basic_test1.log <span style='color:#111;'> 627.58KB </span>","children":null,"spread":false},{"title":"top_sdr8_sim.log <span style='color:#111;'> 788.63KB </span>","children":null,"spread":false},{"title":"top_sdr16_sim.log <span style='color:#111;'> 628.93KB </span>","children":null,"spread":false},{"title":"core_SDR_16BIT_basic_test1.log <span style='color:#111;'> 130.26KB </span>","children":null,"spread":false},{"title":"core_SDR_32BIT_complie.log <span style='color:#111;'> 598B </span>","children":null,"spread":false},{"title":"top_SDR_8BIT_basic_test1.log <span style='color:#111;'> 787.29KB </span>","children":null,"spread":false},{"title":"core_sdr32_sim.log <span style='color:#111;'> 329.77KB </span>","children":null,"spread":false},{"title":"core_sdr8_sim.log <span style='color:#111;'> 131.51KB </span>","children":null,"spread":false},{"title":"core_SDR_8BIT_basic_test1.log <span style='color:#111;'> 130.26KB </span>","children":null,"spread":false},{"title":"top_SDR_32BIT_basic_test1.log <span style='color:#111;'> 425.09KB </span>","children":null,"spread":false},{"title":"top_SDR_16BIT_complie.log <span style='color:#111;'> 687B </span>","children":null,"spread":false},{"title":"core_SDR_32BIT_basic_test1.log <span style='color:#111;'> 328.51KB </span>","children":null,"spread":false},{"title":"core_SDR_8BIT_complie.log <span style='color:#111;'> 599B </span>","children":null,"spread":false},{"title":"core_sdr16_sim.log <span style='color:#111;'> 131.52KB </span>","children":null,"spread":false},{"title":"top_SDR_8BIT_complie.log <span style='color:#111;'> 688B </span>","children":null,"spread":false},{"title":"top_SDR_32BIT_complie.log <span style='color:#111;'> 687B </span>","children":null,"spread":false},{"title":"core_SDR_16BIT_complie.log <span style='color:#111;'> 598B </span>","children":null,"spread":false}],"spread":false},{"title":"test_case","children":null,"spread":false},{"title":"model","children":[{"title":"IS42VM16400K.V <span style='color:#111;'> 75.08KB </span>","children":null,"spread":false},{"title":"mt48lc2m32b2.v <span style='color:#111;'> 47.52KB </span>","children":null,"spread":false},{"title":"mt48lc4m16.v <span style='color:#111;'> 55.10KB </span>","children":null,"spread":false},{"title":"mt48lc8m8a2.v <span style='color:#111;'> 43.22KB </span>","children":null,"spread":false},{"title":"mt48lc8m16a2.v <span style='color:#111;'> 43.16KB </span>","children":null,"spread":false},{"title":"mt48lc4m32b2.v <span style='color:#111;'> 69.17KB </span>","children":null,"spread":false}],"spread":true},{"title":"tb","children":[{"title":"tb_top.sv <span style='color:#111;'> 17.43KB </span>","children":null,"spread":false},{"title":"tb_core.sv <span style='color:#111;'> 19.35KB </span>","children":null,"spread":false}],"spread":true},{"title":"defs","children":null,"spread":false},{"title":"agents","children":null,"spread":false},{"title":"lib","children":null,"spread":false},{"title":"run","children":[{"title":"run_all <span style='color:#111;'> 1.54KB </span>","children":null,"spread":false},{"title":"run_modelsim <span style='color:#111;'> 1.67KB </span>","children":null,"spread":false},{"title":"filelist_core.f <span style='color:#111;'> 327B </span>","children":null,"spread":false},{"title":"filelist_rtl.f <span style='color:#111;'> 305B </span>","children":null,"spread":false},{"title":"read.me <span style='color:#111;'> 893B </span>","children":null,"spread":false},{"title":"compile.modelsim <span style='color:#111;'> 283B </span>","children":null,"spread":false},{"title":"filelist.f <span style='color:#111;'> 322B </span>","children":null,"spread":false},{"title":"run.do <span style='color:#111;'> 9B </span>","children":null,"spread":false},{"title":"filelist_top.f <span style='color:#111;'> 431B </span>","children":null,"spread":false},{"title":"regression_analysis <span style='color:#111;'> 1.36KB </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"rtl","children":[{"title":"core","children":[{"title":"sdrc_define.v <span style='color:#111;'> 814B </span>","children":null,"spread":false},{"title":"sdrc_core.v <span style='color:#111;'> 19.36KB </span>","children":null,"spread":false},{"title":"sdrc_xfr_ctl.v <span style='color:#111;'> 23.28KB </span>","children":null,"spread":false},{"title":"sdrc_bank_fsm.v <span style='color:#111;'> 12.55KB </span>","children":null,"spread":false},{"title":"sdrc_req_gen.v <span style='color:#111;'> 12.77KB </span>","children":null,"spread":false},{"title":"sdrc_bank_ctl.v <span style='color:#111;'> 18.95KB </span>","children":null,"spread":false},{"title":"sdrc_bs_convert.v <span style='color:#111;'> 8.81KB </span>","children":null,"spread":false}],"spread":true},{"title":"filelist_rtl.f <span style='color:#111;'> 222B </span>","children":null,"spread":false},{"title":"top","children":[{"title":"sdrc_top.v <span style='color:#111;'> 13.42KB </span>","children":null,"spread":false}],"spread":true},{"title":"defs","children":null,"spread":false},{"title":"lib","children":[{"title":"sync_fifo.v <span style='color:#111;'> 4.60KB </span>","children":null,"spread":false},{"title":"async_fifo.v <span style='color:#111;'> 8.86KB </span>","children":null,"spread":false}],"spread":true},{"title":"wb2sdrc","children":[{"title":"wb2sdrc.v <span style='color:#111;'> 15.88KB </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"doc","children":[{"title":"sdram_controller_specs.pdf <span style='color:#111;'> 1.22MB </span>","children":null,"spread":false}],"spread":true},{"title":"env","children":null,"spread":false},{"title":"synth","children":[{"title":"constraints","children":[{"title":"sdrc_top.sdc <span style='color:#111;'> 9.20KB </span>","children":null,"spread":false},{"title":"sdrc_synth.sdc <span style='color:#111;'> 3.99KB </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"fpga","children":[{"title":"actel","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}],"spread":true}]