adc7822 verilog实现

[{"title":"（ 45 个子文件 68KB ） adc7822 verilog实现","children":[{"title":"ad7822","children":[{"title":"tb.v <span style='color:#111;'> 1.42KB </span>","children":null,"spread":false},{"title":"display.v <span style='color:#111;'> 3.48KB </span>","children":null,"spread":false},{"title":"da7801.v.bak <span style='color:#111;'> 2.57KB </span>","children":null,"spread":false},{"title":"tb.v.bak <span style='color:#111;'> 1.41KB </span>","children":null,"spread":false},{"title":"convert_table.v <span style='color:#111;'> 3.92KB </span>","children":null,"spread":false},{"title":"key.v.bak <span style='color:#111;'> 3.54KB </span>","children":null,"spread":false},{"title":"key.v <span style='color:#111;'> 3.56KB </span>","children":null,"spread":false},{"title":"adc_behavor.v.bak <span style='color:#111;'> 1.79KB </span>","children":null,"spread":false},{"title":"vsim.wlf <span style='color:#111;'> 40.00KB </span>","children":null,"spread":false},{"title":"work","children":[{"title":"adc_display","children":[{"title":"verilog.asm <span style='color:#111;'> 15.05KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 865B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 2.78KB </span>","children":null,"spread":false}],"spread":true},{"title":"adc_behavor","children":[{"title":"verilog.asm <span style='color:#111;'> 9.90KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 418B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 1.49KB </span>","children":null,"spread":false}],"spread":true},{"title":"dac7801","children":[{"title":"verilog.asm <span style='color:#111;'> 11.67KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 706B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 1.90KB </span>","children":null,"spread":false}],"spread":true},{"title":"testbench","children":[{"title":"verilog.asm <span style='color:#111;'> 9.24KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 78B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 1.27KB </span>","children":null,"spread":false}],"spread":false},{"title":"ad7822","children":[{"title":"verilog.asm <span style='color:#111;'> 12.41KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 1.04KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 2.45KB </span>","children":null,"spread":false}],"spread":false},{"title":"key_control","children":[{"title":"verilog.asm <span style='color:#111;'> 14.91KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 418B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 2.62KB </span>","children":null,"spread":false}],"spread":false},{"title":"convert_table","children":[{"title":"verilog.asm <span style='color:#111;'> 13.65KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 660B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 3.48KB </span>","children":null,"spread":false}],"spread":false},{"title":"adc_fsm","children":[{"title":"verilog.asm <span style='color:#111;'> 30.13KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 866B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 4.22KB </span>","children":null,"spread":false}],"spread":false},{"title":"_info <span style='color:#111;'> 1.39KB </span>","children":null,"spread":false}],"spread":true},{"title":"ad7822.cr.mti <span style='color:#111;'> 1.40KB </span>","children":null,"spread":false},{"title":"wave.do <span style='color:#111;'> 1.70KB </span>","children":null,"spread":false},{"title":"ad7822.v.bak <span style='color:#111;'> 3.58KB </span>","children":null,"spread":false},{"title":"adc_behavor.v <span style='color:#111;'> 1.81KB </span>","children":null,"spread":false},{"title":"convert_table.v.bak <span style='color:#111;'> 3.90KB </span>","children":null,"spread":false},{"title":"fsm.v.bak <span style='color:#111;'> 6.17KB </span>","children":null,"spread":false},{"title":"ad7822.mpf <span style='color:#111;'> 22.67KB </span>","children":null,"spread":false},{"title":"fsm.v <span style='color:#111;'> 6.20KB </span>","children":null,"spread":false},{"title":"display.v.bak <span style='color:#111;'> 3.46KB </span>","children":null,"spread":false},{"title":"da7801.v <span style='color:#111;'> 2.58KB </span>","children":null,"spread":false},{"title":"ad7822.v <span style='color:#111;'> 3.59KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]